Patents by Inventor Kishore Kumar

Kishore Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230307053
    Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 28, 2023
    Inventors: Paing Z. Htet, Akira Goda, Eric N. Lee, Jeffrey S. McNeil, Junwyn A. Lacsao, Kishore Kumar Muchherla, Sead Zildzic, Violante Moschiano
  • Publication number: 20230305744
    Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 28, 2023
    Inventors: Kishore Kumar Muchherla, Eric N. Lee, Jeffrey S. McNeil, Jonathan S. Parry, Lakshmi Kalpana Vakati
  • Patent number: 11768619
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a first block family comprising a first set of blocks, wherein the first block family comprises a plurality of blocks that have been programmed within at least one of a specified time window or a specified temperature window; identify a second block family comprising a second set of blocks; and responsive to a determining that a threshold criterion is satisfied, combine the first block family and the second block family by appending, to first block family metadata of the first block family, a record referencing the second set of blocks.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Shane Nowell
  • Publication number: 20230298081
    Abstract: A bundle generation engine provides recommendations for an item and at least one compatible item. Upon receiving an item listing for an item at a listing platform, the bundle generation engine determines that unstructured text of an item description for the item listing includes one or more compatible items. For example, the bundle generation engine may use a classification model to determine the unstructured text includes the one or more compatible items. Based on determining that the unstructured text includes the one or more compatible items, the bundle generation engine identifies one or more identifiers within the unstructured text of the item description. For example, the identifiers may be model identifiers or brand identifiers. In aspects, the identifiers are identified using one or more natural language processing models. A bundle recommendation is provided to a user device based on the one or more identifiers.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Inventors: Kishore Kumar MOHAN, Ramesh PERIYATHAMBI, Lakshimi DURAIVENKATESH
  • Publication number: 20230297470
    Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 21, 2023
    Inventors: Mustafa N. Kaynak, Kishore Kumar Muchherla, Sivagnanam Parthasarathy, James Fitzpatrick, Mark A. Helm
  • Patent number: 11762345
    Abstract: Real-time dynamic optimization of a process model in an online model-based process control computing environment. A mixed integer nonlinear programming (MINLP) solver utilizes grouping of first-principle model units to implement constraints of the underlying process. A group identifier parameter and a group complement parameter enable the grouping behavior through association with the first-principles model units.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: September 19, 2023
    Assignee: AVEVA SOFTWARE, LLC
    Inventors: Rajkumar Vedam, James Jude Kattapuram, Kishore Kumar Hemachandran, Sankararao Boddupalli, Pranav Bhaswanth Madabhushi, Gareth Hillier, Mallikarjun Avanna Lavate, Detong Zhang, Purt Tanartkit
  • Patent number: 11762767
    Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Giuseppina Puzzilli, Vamsi Pavan Rayaprolu, Ashutosh Malshe, James Fitzpatrick, Shyam Sunder Raghunathan, Violante Moschiano, Tecla Ghilardi
  • Publication number: 20230289062
    Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 14, 2023
    Inventors: Jeffrey S. McNeil, Jonathan S. Parry, Ugo Russo, Akira Goda, Kishore Kumar Muchherla, Violante Moschiano, Niccolo' Righetti, Silvia Beltrami
  • Patent number: 11755472
    Abstract: A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale
  • Patent number: 11756594
    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: September 12, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Kishore Kumar Muchherla, Jeffrey S. McNeil, Jung-Sheng Hoei
  • Publication number: 20230282293
    Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.
    Type: Application
    Filed: February 15, 2023
    Publication date: September 7, 2023
    Inventors: Kishore Kumar Muchherla, Mustafa N Kaynak, Sampath K Ratnam, Shane Nowell, Peter Feeley, Sivagnanam Parthasarathy
  • Patent number: 11748013
    Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Mustafa N. Kaynak, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley, Karl D. Schuh
  • Patent number: 11744844
    Abstract: Novel selective estrogen receptor degraders (SERDs) according to the formula: and pharmaceutically acceptable salt thereof and pharmaceutical compositions thereof, wherein R is selected from
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: September 5, 2023
    Assignee: Eli Lilly and Company
    Inventors: Kenneth Charles Cassidy, Kishore Kumar Katyayan
  • Patent number: 11740805
    Abstract: A distribution statistic is generated for a data block of a memory component based on a reliability statistic for memory cells sampled in the data block. The distribution statistic is indicative of at least one of a uniformity or a non-uniformity of read disturb stress on the sampled memory cells. At least a subset of the data block is relocated to another data block of the memory component in view of the distribution statistic.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Vamsi Vamsi Rayaprolu, Harish R. Singidi
  • Patent number: 11740957
    Abstract: A failure of a first memory access operation is detected at a memory device. Responsive to the detection, a first error control operation and a second error control operation are performed. In response to a determination that the second error control operation has remedied the failed first memory access operation, the second error control operation is associated with a second priority which is higher than a first priority associated with the first error control operation.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Harish R. Singidi, Kishore Kumar Muchherla, Ashutosh Malshe, Xiangang Luo
  • Patent number: 11735254
    Abstract: A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a data structure mapping block identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block of the memory device, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block, and reading, using the determined set of read levels, data from the block of the memory device.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shane Nowell, Steven Michael Kientz, Michael Sheperek, Mustafa N Kaynak, Kishore Kumar Muchherla, Larry J Koudele, Bruce A Liikanen
  • Patent number: 11727994
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to program a first block in a first die of the memory device and a second block in a second die of the memory device, wherein the first die and the second die are assigned to a die group; and associate the die group with a threshold voltage offset bin.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Larry J. Koudele
  • Patent number: 11726689
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to determine that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families satisfy a proximity condition; determine whether the first block family and the second block family meet a time-based combining criterion corresponding to the proximity condition; and responsive to determining that the first block family and the second block family meet the time-based combining criterion, merge the first block family and the second block family.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shane Nowell, Michael Sheperek, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla
  • Patent number: D997111
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: August 29, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Martin Lee Riker, Fuhong Zhang, Lanlan Zhong, Kishor Kumar Kalathiparambil
  • Patent number: D998575
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: September 12, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Martin Lee Riker, Fuhong Zhang, Lanlan Zhong, Kishor Kumar Kalathiparambil