Patents by Inventor Kiyohiko Maeda

Kiyohiko Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060150904
    Abstract: A CVD device has a reaction furnace (39) for processing a wafer (1); a seal cap (20) for sealing the reaction furnace (39) hermetically; an isolation flange (42) opposite to the seal cap (20); a small chamber (43) formed by the seal cap (20), the isolation flange (42), and the wall surface in the reaction furnace (39); a feed pipe (19b) for supplying a first gas to the small chamber (43); an outflow passage (42a) provided in the small chamber (43) for allowing the first gas to flow into the reaction furnace (39); and a feed pipe (19a) provided downstream from the outflow passage (42a) for supplying a second gas into the reaction furnace (39). Byproducts such as NH4Cl are prevented from adhering to low temperature sections such as the furnace opening and therefore the semiconductor device production yield is therefore increased.
    Type: Application
    Filed: February 20, 2004
    Publication date: July 13, 2006
    Inventors: Takashi Ozaki, Tomoshi Taniyama, Hiroshi Unami, Kiyohiko Maeda, Shinya Morita, Yoshikazu Takashima, Sadao Hisakado
  • Publication number: 20060121746
    Abstract: A semiconductor device manufacturing method comprises a first step of forming, by a thermal chemical vapor deposition method, a silicon nitride film on an object disposed in a reaction container, with bis tertiary butyl amino silane and NH3 flowing into the reaction container, and a second step of removing silicon nitride formed in the reaction container, with NF3 gas flowing into the reaction container.
    Type: Application
    Filed: January 11, 2006
    Publication date: June 8, 2006
    Inventors: Norikazu Mizuno, Kiyohiko Maeda
  • Patent number: 6716772
    Abstract: A semiconductor device manufacturing apparatus which forms silicon nitride films on a plurality of substrates by thermal chemical vapor deposition. The semiconductor device manufacturing apparatus includes a vertical reaction tube, a substrate holder, and gas supplies. The vertical reaction tube has an inner wall. The substrate holder is for holding the plurality of substrates in the vertical reaction tube with the plurality of substrates being vertically stacked with a distance “a” between adjacent substrates of the plurality of substrates and a distance “b” between edges of the plurality of substrates and the inner wall of the vertical reaction tube being maintained substantially equal to each other.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: April 6, 2004
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Norikazu Mizuno, Kiyohiko Maeda
  • Patent number: 6524650
    Abstract: Substrate processing apparatus and method, by which an outside air and a gas-phase backward flow are restrained from entering the inside of a reaction chamber during the inside of a reaction chamber is opened to the outside through a substrate carrying-in/carrying-out opening. This substrate processing apparatus, for example, a vertical CVD apparatus (200) has a gas supply system (240) and a bypass line (264). The gas supply system (240) supplies an inert gas to a space (3a) between an outer tube (1A) and an inner tube (2A) of a reaction furnace (211) in a boat loading term and a boat unloading term. The bypass line (264) exhausts an atmosphere from a reaction chamber (1a) by performing a slow exhaust operation in the boat loading term and the boat unloading term.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: February 25, 2003
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Takashi Shimahara, Naoto Nakamura, Ichiro Sakamoto, Kiyohiko Maeda
  • Publication number: 20020197890
    Abstract: A semiconductor device manufacturing method comprises a step of forming, by thermal chemical vapor deposition method, silicon nitride films on a plurality of substrates stacked in a reaction tube, with bis tertiary butyl amino silane and NH3 flowing into the reaction tube accommodating the stacked substrates, wherein the silicon nitride films are formed on the substrates in a state in which a distance “a” between adjacent the substrates and a distance “b” between edges of the substrates and an inner wall of the reaction tube are maintained substantially equal to each other.
    Type: Application
    Filed: August 20, 2002
    Publication date: December 26, 2002
    Applicant: KOKUSAI ELECTRIC CO., LTD.
    Inventors: Norikazu Mizuno, Kiyohiko Maeda
  • Patent number: 6486083
    Abstract: A semiconductor device manufacturing method including a step of forming, by thermal chemical vapor deposition, silicon nitride films on a plurality of substrates vertically stacked in a vertical reaction tube having an inner wall. Bis tertiary butyl amino silane and NH3 flows into the vertical reaction tube and flows vertically from one end of the plurality of substrates to an opposing end of the plurality of substrates without flowing into the vertical reaction tube through the inner wall at a height between the one end and the opposing end of the plurality of substrates. The silicon nitride films are formed on the plurality of substrates in a state in which a distance “a” between adjacent substrates of the plurality of substrates and a distance “b” between edges of the plurality of substrates and the inner wall of the vertical reaction tube are maintained substantially equal to each other.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: November 26, 2002
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Norikazu Mizuno, Kiyohiko Maeda
  • Patent number: 6139642
    Abstract: A substrate processing apparatus and method restrains outside air and gas-phase backward flow from entering the inside of a reaction chamber during a time period that the inside of the reaction chamber is opened to the outside through a substrate carrying-in/carrying-out opening. The substrate processing apparatus can comprise, for example, a vertical CVD apparatus having a gas supply system and a bypass line. The gas supply system supplies inert gas to a space between an outer tube and an inner tube of a reaction furnace during a boat loading period and a boat unloading period. The bypass line exhausts the atmosphere from the reaction chamber by a slow exhaust operation during the boat loading period and the boat unloading period.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: October 31, 2000
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Takashi Shimahara, Naoto Nakamura, Ichiro Sakamoto, Kiyohiko Maeda
  • Patent number: 5902103
    Abstract: A vertical furnace for use in a semiconductor manufacturing apparatus, which comprises a heater, an outer tube, an inner tube, all being disposed concentrically in a multi-layered fashion, a boat adapted to be introduced into the inner tube with a wafer loaded thereon, and a boat cover disposed internally of the inner tube concentrically therewith. The boat cover is comprised of a boat cover body and an auxiliary cover plate connected to said boat cover body with a given gap therebetween, the boat cover body having a predetermined number of slit apertures extending in a generator direction thereof, the auxiliary cover plate being disposed to cover the slit apertures. The introduced reactive gas flows in branched streams, one flowing through the inside of the boat cover and the other flowing in past the boat cover, whereby the film deposited on the wafer is improved in uniformity and homogeneity.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: May 11, 1999
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Kiyohiko Maeda, Satoshi Kakizaki, Tomoshi Taniyama, Hidehiro Yanagawa, Ken-ichi Suzaki