Patents by Inventor Kiyoshi Arita

Kiyoshi Arita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050279459
    Abstract: In a plasma treating apparatus for carrying out a plasma treatment over a silicon wafer 6 having a protective tape 6a stuck to a circuit formation face, the silicon wafer 6 is mounted on a mounting surface 3d which is provided on an upper surface of a lower electrode 3 formed of a conductive metal with the protective tape 6a turned toward the mounting surface 3d. When a DC voltage is to be applied to the lower electrode 3 by a DC power portion 18 for electrostatic adsorption to adsorb and hold the silicon wafer 6 onto the lower electrode 3 in the plasma treatment, the protective tape 6a is utilized as a dielectric for the electrostatic adsorption. Consequently, the dielectric can be thinned as much as possible and the silicon wafer 6 can be held by a sufficient electrostatic holding force.
    Type: Application
    Filed: June 8, 2005
    Publication date: December 22, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Junichi Terayama
  • Patent number: 6969669
    Abstract: In the process of plasma dicing in which the semiconductor wafer 6 is divided into individual pieces by plasma, SiO2 layer 42 and the protective layer 43, which are formed covering the active layer 41, are utilized as an etching stop layer for absorbing fluctuation of the etching rate in the first plasma dicing step in which the wafer base layer 40 is etched and cut off. Next, the second plasma dicing step is conducted in which the etching stop layer exposed by the first plasma dicing step is cut off with plasma of the second plasma generating gas capable of etching at a high etching rate, and heat damage is prevented which is caused when the protective sheet 30 is exposed to plasma for a long period of time.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: November 29, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoshi Arita
  • Publication number: 20050247404
    Abstract: In a plasma processing apparatus for plasma-processing a silicon wafer 6 to which a protective film 6a is stuck in a state that the silicon wafer 6 is held by a first electrode 3 by electrostatic absorption and is being cooled, the top surface 3g of the first electrode 3 consists of a top surface central area A that is inside a boundary line P2 that is distant inward by a prescribed length from the outer periphery P1 of the silicon wafer 6 and in which the conductor is exposed, and a ring-shaped top surface peripheral area B that surrounds the top surface central area A and in which the conductor is covered with an insulating coating 3f. This structure makes it possible to hold the silicon wafer 6 by sufficient electrostatic holding force by bringing the silicon wafer 6 into direct contact with the conductor and to increase the cooling efficiency by virtue of heat conduction from the silicon wafer 6 to the first electrode 3.
    Type: Application
    Filed: June 8, 2005
    Publication date: November 10, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuhiro Iwai, Kiyoshi Arita
  • Publication number: 20050173065
    Abstract: In a method of manufacturing a semiconductor device by dividing a semiconductor wafer 6, on which a plurality of semiconductor elements are formed, into individual pieces of the semiconductor elements, after thickness of a reverse face of a circuit formation face 6a is reduced by machining, a mask to determine cutting lines 31b is formed by a resist film 31a, and the semiconductor wafer 6 is divided into individual pieces of semiconductor elements 6c by conducting plasma etching on portions of the cutting lines 31b when plasma is exposed from the mask side, and then the resist film 31a is removed by plasma, and further a micro-crack layer 6b generated on the machined face is removed by plasma etching. A series of the above plasma processing is executed by the same plasma processing apparatus.
    Type: Application
    Filed: April 8, 2005
    Publication date: August 11, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoshi Arita
  • Patent number: 6921720
    Abstract: In a plasma treating apparatus for carrying out a plasma treatment over a silicon wafer 6 having a protective tape 6a stuck to a circuit formation face, the silicon wafer 6 is mounted on a mounting surface 3d which is provided on an upper surface of a lower electrode 3 formed of a conductive metal with the protective tape 6a turned toward the mounting surface 3d. When a DC voltage is to be applied to the lower electrode 3 by a DC power portion 18 for electrostatic adsorption to adsorb and hold the silicon wafer 6 onto the lower electrode 3 in the plasma treatment, the protective tape 6a is utilized as a dielectric for the electrostatic adsorption. Consequently, the dielectric can be thinned as much as possible and the silicon wafer 6 can be held by a sufficient electrostatic holding force.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: July 26, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Junichi Terayama
  • Patent number: 6897128
    Abstract: In a method of manufacturing a semiconductor device by dividing a semiconductor wafer 6, on which a plurality of semiconductor elements are formed, into individual pieces of the semiconductor elements, after thickness of a reverse face of a circuit formation face 6a is reduced by machining, a mask to determine cutting lines 31b is formed by a resist film 31a, and the semiconductor wafer 6 is divided into individual pieces of semiconductor elements 6c by conducting plasma etching on portions of the cutting lines 31b when plasma is exposed from the mask side, and then the resist film 31a is removed by plasma, and further a micro-crack layer 6b generated on the machined face is removed by plasma etching. A series of the above plasma processing is executed by the same plasma processing apparatus.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: May 24, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoshi Arita
  • Publication number: 20050072766
    Abstract: In the process of plasma dicing in which the semiconductor wafer 6 is divided into individual pieces by plasma, SiO2 layer 42 and the protective layer 43, which are formed covering the active layer 41, are utilized as an etching stop layer for absorbing fluctuation of the etching rate in the first plasma dicing step in which the wafer base layer 40 is etched and cut off. Next, the second plasma dicing step is conducted in which the etching stop layer exposed by the first plasma dicing step is cut off with plasma of the second plasma generating gas capable of etching at a high etching rate, and heat damage is prevented which is caused when the protective sheet 30 is exposed to plasma for a long period of time.
    Type: Application
    Filed: January 21, 2004
    Publication date: April 7, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoshi Arita
  • Patent number: 6867146
    Abstract: A method of plasma-processing a silicon-based substrate provides a mirror-like etched surface of the substrate. A silicon wafer having a protective tape affixed to a circuit-formed side of the wafer is mounted on a mounting unit disposed within a process chamber of a plasma processing apparatus while the protective tape contacts on the mounting unit. The surface of the silicon wafer is kept at a temperature of 40° C. or above when the surface of the substrate is etched by plasma generated by plasma discharge in plasma-generating gas including fluorine-containing gas fed into the process chamber. This suppressing adhesion and accumulation of a reaction product of the fluorine-containing gas with respect to the surface to be etched, and consequently, provides the surface with uniform etching.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: March 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai
  • Patent number: 6852572
    Abstract: The method of manufacturing a semiconductor device of the present invention comprises: forming a resin layer on a surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, forming through-holes on the resin layer, a first cutting of either the semiconductor wafer or the resin layer, mounting conductive balls on the through-hole, connecting the conductive ball to electrodes of the semiconductor element, and a second cutting for dividing the wafer into each piece of semiconductor devices. With the processes of the present invention, conductive balls can be easily and effectively mounted on a wafer under optimum conditions, without failure such as slipping or falling down from the required position. This fact contributes to an increased efficiency and a good productivity in the production of semiconductor devices.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: February 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Haji, Shoji Sakemi, Mitsuru Ozono, Tadahiko Sakai, Kiyoshi Arita
  • Patent number: 6784112
    Abstract: A surface treatment method for thinning a silicon based substrate obtains a milky-dull color on an overall surface uniformly of the silicon based substrate. To be more specific, a surface opposite to a circuit-formed surface is mechanically polished, then the surface is etched using inert gas such as argon gas for producing plasma. This etching forms micro dimples uniformly on the surface. Next, the surface is further etched using fluorine based gas for producing plasma. This etching obtains a milky-dull color uniformly on the surface. As a result, printed marks on the surface can be read with ease, and pick-up errors in die-bonding can be reduced.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: August 31, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
  • Publication number: 20040121611
    Abstract: In a method of cutting a semiconductor wafer in which the semiconductor wafer 6 is cut by plasma etching, a protective sheet 30 on which a metallic layer 30b, a plasma etching rate of which is low, is formed on one face of an insulating sheet 30a is stuck on to a circuit forming face 6a by an adhesive layer 30c, and plasma is exposed onto an opposite side to the circuit forming face 6a from a mask side which is formed by covering regions except for cutting lines 31b with a resist film 31a so as to conduct plasma etching on portions of the cutting lines. Due to the above structure, it is possible to use the metallic layer as an etching stop layer for suppressing the progress of etching. Therefore, fluctuation of the progress of etching can be avoided and heat damage caused on the protective sheet can be prevented.
    Type: Application
    Filed: December 10, 2003
    Publication date: June 24, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoshi Arita
  • Publication number: 20040102025
    Abstract: In a method of manufacturing a semiconductor device by dividing a semiconductor wafer 6, on which a plurality of semiconductor elements are formed, into individual pieces of the semiconductor elements, after thickness of a reverse face of a circuit formation face 6a is reduced by machining, a mask to determine cutting lines 31b is formed by a resist film 31a, and the semiconductor wafer 6 is divided into individual pieces of semiconductor elements 6c by conducting plasma etching on portions of the cutting lines 31b when plasma is exposed from the mask side, and then the resist film 31a is removed by plasma, and further a micro-crack layer 6b generated on the machined face is removed by plasma etching. A series of the above plasma processing is executed by the same plasma processing apparatus.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 27, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiyoshi Arita
  • Patent number: 6723651
    Abstract: A method of plasma processing a silicon-containing object to be processed at a high etching rate without causing a surface of the object to have a hazy appearance, so that this surface can have an excellent visual quality. In the plasma processing method of etching the surface of the semiconductor wafer, gas containing sulfur hexafluoride and helium is used as a plasma-generating gas. A fluorine radical as an active substance which reacts with silicon of the surface of the semiconductor wafer, gaseous silicon tetrafluoride yielded by the reaction and a compound (SFn) of fluorine and sulfur that is generated as a reaction product are removed by the helium gas functioning as carrier gas. The helium gas prevents the reaction product from adhering to the surface of the wafer again.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: April 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Shoji Sakemi
  • Publication number: 20040050496
    Abstract: In a plasma processing apparatus for plasma-processing a silicon wafer 6 to which a protective film 6a is stuck in a state that the silicon wafer 6 is held by a first electrode 3 by electrostatic absorption and is being cooled, the top surface 3g of the first electrode 3 consists of a top surface central area A that is inside a boundary line P2 that is distant inward by a prescribed length from the outer periphery P1 of the silicon wafer 6 and in which the conductor is exposed, and a ring-shaped top surface peripheral area B that surrounds the top surface central area A and in which the conductor is covered with an insulating coating 3f. This structure makes it possible to hold the silicon wafer 6 by sufficient electrostatic holding force by bringing the silicon wafer 6 into direct contact with the conductor and to increase the cooling efficiency by virtue of heat conduction from the silicon wafer 6 to the first electrode 3.
    Type: Application
    Filed: July 17, 2003
    Publication date: March 18, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuhiro Iwai, Kiyoshi Arita
  • Publication number: 20030082914
    Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.
    Type: Application
    Filed: December 11, 2002
    Publication date: May 1, 2003
    Inventors: Yutaka Koma, Kiyoshi Arita, Hiroshi Haji, Tetsuhiro Iwai
  • Publication number: 20030037882
    Abstract: In a plasma treating apparatus for carrying out a plasma treatment over a silicon wafer 6 having a protective tape 6a stuck to a circuit formation face, the silicon wafer 6 is mounted on a mounting surface 3d which is provided on an upper surface of a lower electrode 3 formed of a conductive metal with the protective tape 6a turned toward the mounting surface 3d. When a DC voltage is to be applied to the lower electrode 3 by a DC power portion 18 for electrostatic adsorption to adsorb and hold the silicon wafer 6 onto the lower electrode 3 in the plasma treatment, the protective tape 6a is utilized as a dielectric for the electrostatic adsorption. Consequently, the dielectric can be thinned as much as possible and the silicon wafer 6 can be held by a sufficient electrostatic holding force.
    Type: Application
    Filed: August 26, 2002
    Publication date: February 27, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Junichi Terayama
  • Patent number: 6511917
    Abstract: A plasma treatment apparatus according to the present invention includes a vacuum chamber, an upper electrode and a lower electrode disposed in the vacuum chamber, a high-frequency power supply for applying a high-frequency voltage, a space adjusting device for adjusting the spacing between the two electrodes, and a workpiece-transfer-device for transferring to and from a space between the two electrodes. The plasma treatment apparatus can decrease the spacing between the two electrodes and thereby increase the etching rate. Further, the workpiece can be easily transferred to and from the space between the two electrodes by opening the spacing.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: January 28, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Haji, Kiyoshi Arita
  • Patent number: 6511895
    Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: January 28, 2003
    Assignees: Disco Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Koma, Kiyoshi Arita, Hiroshi Haji, Tetsuhiro Iwai
  • Publication number: 20020197877
    Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion 18a formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member 17 for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion 18b formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.
    Type: Application
    Filed: June 21, 2002
    Publication date: December 26, 2002
    Applicant: Matsushita Electric Industrial Co. Ltd.
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
  • Publication number: 20020195202
    Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.
    Type: Application
    Filed: June 21, 2002
    Publication date: December 26, 2002
    Applicant: Matsushita Electric Industrial Co., LTD
    Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi, Taiji Matano, Nobuhiro Satou