Patents by Inventor Kiyotaka Miyano

Kiyotaka Miyano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6417551
    Abstract: The present invention provides a method of manufacturing a semiconductor device, comprising the steps of forming a gate insulating film, on a semiconductor substrate, forming a gate electrode containing a refractory metal layer on the gate insulation film, and heat-processing the semiconductor substrate in an atmosphere containing water vapor and hydrogen, to lessen a damage caused to a portion of the semiconductor substrate, which is located close to an end portion of the gate electrode. The heat-processing step is carried out while controlling a vapor pressure of a refractory metal oxo-acid generated on a surface of the high-melting metal layer.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: July 9, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyotaka Miyano
  • Patent number: 6395621
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate a exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: May 28, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Publication number: 20020034864
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Application
    Filed: December 3, 2001
    Publication date: March 21, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Patent number: 6346732
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: February 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Patent number: 6335251
    Abstract: A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: January 1, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Tomohiro Saito
  • Publication number: 20010023120
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Application
    Filed: March 9, 2001
    Publication date: September 20, 2001
    Inventors: Yoshitaka Tsunashima, Seiji Inumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Publication number: 20010023108
    Abstract: A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate.
    Type: Application
    Filed: April 3, 2001
    Publication date: September 20, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Tomohiro Saito
  • Publication number: 20010010966
    Abstract: The present invention provides a method of manufacturing a semiconductor device, comprising the steps of forming a gate insulating film, on a semiconductor substrate, forming a gate electrode containing a refractory metal layer on the gate insulation film, and heat-processing the semiconductor substrate in an atmosphere containing water vapor and hydrogen, to lessen a damage caused to a portion of the semiconductor substrate, which is located close to an end portion of the gate electrode. The heat-processing step is carried out while controlling a vapor pressure of a refractory metal oxo-acid generated on a surface of the high-melting metal layer.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 2, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kiyotaka Miyano
  • Patent number: 6232641
    Abstract: A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: May 15, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Tomohiro Saito
  • Patent number: 6228752
    Abstract: The present invention provides a method of manufacturing a semiconductor device, comprising the steps of forming a gate insulating film, on a semiconductor substrate, forming a gate electrode containing a refractory metal layer on the gate insulation film, and heat-processing the semiconductor substrate in an atmosphere containing water vapor and hydrogen, to lessen a damage caused to a portion of the semiconductor substrate, which is located close to an end portion of the gate electrode. The heat-processing step is carried out while controlling a vapor pressure of a refractory metal oxo-acid generated on a surface of the high-melting metal layer.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: May 8, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyotaka Miyano
  • Patent number: 6184083
    Abstract: A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: February 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Kiyotaka Miyano, Yukihiro Ushiku
  • Patent number: 6162741
    Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: December 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
  • Patent number: 6133150
    Abstract: A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: October 17, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Nakajima, Yasushi Akasaka, Kiyotaka Miyano, Kyoichi Suguro
  • Patent number: 5907188
    Abstract: A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: May 25, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Nakajima, Yasushi Akasaka, Kiyotaka Miyano, Kyoichi Suguro