Patents by Inventor Kiyotaka Miyano

Kiyotaka Miyano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6924518
    Abstract: There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 2, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihiko Iinuma, Ichiro Mizushima, Mitsuaki Izuha, Kiyotaka Miyano, Kyoichi Suguro
  • Publication number: 20050130418
    Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.
    Type: Application
    Filed: February 2, 2005
    Publication date: June 16, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
  • Patent number: 6893980
    Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: May 17, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
  • Patent number: 6893928
    Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: May 17, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Toshihiko Iinuma, Kiyotaka Miyano
  • Patent number: 6891232
    Abstract: A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: May 10, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Kazuya Ohuchi, Ichiro Mizushima
  • Publication number: 20050035413
    Abstract: A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.
    Type: Application
    Filed: September 23, 2004
    Publication date: February 17, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Kazuya Ohuchi, Ichiro Mizushima
  • Publication number: 20050014354
    Abstract: A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1-30 atomic % of chlorine.
    Type: Application
    Filed: August 12, 2004
    Publication date: January 20, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Masayuki Tanaka, Kiyotaka Miyano, Shigehiko Saida
  • Publication number: 20050006686
    Abstract: A semiconductor device having a trench capacitor is disclosed. The trench is formed on the surface of a semiconductor substrate. A first insulating film is formed on the side wall of the trench and a semiconductor film is buried in the trench. The first insulating film and the semiconductor film located in the upper part of the trench are etched and a second insulating film is deposited on the exposed side wall. The semiconductor film and the first insulating film are etched and a plate electrode is formed on the exposed side wall. A capacitor insulating film is formed on the plate electrode and a storage electrode is buried within the trench. The structure provides a semiconductor device having fewer memory cell defects.
    Type: Application
    Filed: February 4, 2004
    Publication date: January 13, 2005
    Inventors: Shigehiko Saida, Kiyotaka Miyano, Takashi Nakao
  • Publication number: 20050006637
    Abstract: There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.
    Type: Application
    Filed: December 23, 2003
    Publication date: January 13, 2005
    Inventors: Toshihiko Iinuma, Ichiro Mizushima, Mitsuaki Izuha, Kiyotaka Miyano, Kyoichi Suguro
  • Publication number: 20050006675
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Application
    Filed: August 11, 2004
    Publication date: January 13, 2005
    Inventors: Yoshitaka Tsunashima, Seiji Ihumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Publication number: 20040183131
    Abstract: A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.
    Type: Application
    Filed: May 16, 2003
    Publication date: September 23, 2004
    Inventors: Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima
  • Patent number: 6784508
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 31, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Seiji Inumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Publication number: 20040124476
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulating film formed on a channel region between the source/drain regions, a gate electrode formed on the gate insulating film, and a sidewall insulating film formed on a sidewall surface of the gate electrode, wherein the gate electrode is made of SiGe, the sidewall insulating film is an insulating film obtained by oxidizing the sidewall surface of the gate electrode, and the sidewall insulating film contains silicon oxide as a main component.
    Type: Application
    Filed: November 13, 2003
    Publication date: July 1, 2004
    Inventor: Kiyotaka Miyano
  • Publication number: 20040070045
    Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
    Type: Application
    Filed: July 22, 2003
    Publication date: April 15, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
  • Publication number: 20030211713
    Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
    Type: Application
    Filed: April 4, 2003
    Publication date: November 13, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
  • Publication number: 20030173617
    Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
    Type: Application
    Filed: March 18, 2003
    Publication date: September 18, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Toshihiko Iinuma, Kiyotaka Miyano
  • Patent number: 6617226
    Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kyoioni Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
  • Publication number: 20030141549
    Abstract: A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.
    Type: Application
    Filed: January 30, 2003
    Publication date: July 31, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiyotaka Miyano, Kazuya Ohuchi, Ichiro Mizushima
  • Publication number: 20030127695
    Abstract: A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1-30 atomic % of chlorine.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 10, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshio Ozawa, Masayuki Tanaka, Kiyotaka Miyano, Shigehiko Saida
  • Patent number: 6570217
    Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: May 27, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Toshihiko Iinuma, Kiyotaka Miyano