Patents by Inventor Kiyotaka Miyano

Kiyotaka Miyano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130248977
    Abstract: A non-volatile semiconductor storage device according to one embodiment of the present application has a memory cell array that includes at least one memory string, a first select transistor, and a second select transistor on a substrate in a lattice form. The first select transistor is electrically connected to a first end of the memory string. The second select transistor is electrically connected to a second end of the memory string. The memory string includes a columnar portion. Multiple memory cells are formed in the columnar portion by multiple conductive layers, multiple insulating layers, a first insulating layer, a charge accumulation layer, a second insulating layer, and a memory channel layer, and are serially connected. The memory channel layer comprises silicon germanium doped with phosphorus.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinji MORI, Jun FUJIKI, Kiyotaka MIYANO
  • Patent number: 8476708
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion. The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Masaru Kito, Kiyotaka Miyano, Shinji Mori, Ichiro Mizushima
  • Patent number: 8426285
    Abstract: An ion implantation is performed to implant ions into a silicon substrate, and a microwave irradiation is performed to irradiate the silicon substrate with microwaves after the ion implantation. After the microwave irradiation, the silicon substrate is transferred to a heat-treatment apparatus, where the silicon substrate is treated with heat by being irradiated with light having a pulse width ranging from 0.1 milliseconds to 100 milliseconds, both inclusive.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Yoshino, Kiyotaka Miyano, Tomonori Aoyama
  • Publication number: 20130075830
    Abstract: In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves.
    Type: Application
    Filed: July 13, 2012
    Publication date: March 28, 2013
    Inventors: Kiyotaka MIYANO, Toshitaka MIYATA
  • Publication number: 20130075844
    Abstract: A semiconductor device according to the present embodiment comprises a lower electrode provided above a semiconductor substrate and made of metal, an upper electrode provided above the lower electrode and made of metal, and a crystal layer provided between the lower electrode and the upper electrode. A thickness of each of the lower electrode and the upper electrode is smaller than a thickness of a skin layer deriving from a skin effect corresponding to a frequency of a microwave used to crystallize the crystal layer.
    Type: Application
    Filed: July 11, 2012
    Publication date: March 28, 2013
    Inventors: Kiyotaka Miyano, Tomonori Aoyama
  • Patent number: 8383452
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Kiyotaka Miyano, Yusuke Oshiki
  • Patent number: 8377732
    Abstract: In one embodiment, a method of manufacturing a back side illuminated imaging device includes forming a semiconductor detection device and a peripheral circuit device on a semiconductor substrate, and bonding the semiconductor substrate onto a holding substrate via the semiconductor detection device and the peripheral circuit device. The method further includes removing the semiconductor substrate from the holding substrate to transfer the semiconductor detection device and the peripheral circuit device onto the holding substrate. The method further includes forming an amorphous semiconductor layer in which impurities are introduced, on the semiconductor detection device transferred onto the holding substrate, and annealing the amorphous semiconductor layer by using a microwave.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Oshiki, Kiyotaka Miyano
  • Publication number: 20130023102
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a gate electrode on a channel region in a silicon substrate via a gate insulation film; forming a source region and a drain region in the silicon substrate so as to sandwich the channel region along a channel direction by injecting desired impurities to the silicon substrate; forming amorphous regions containing the impurities on surfaces of the source region and the drain region by amorphousizing the surfaces of the source region and the drain region; forming nickel films on the amorphous regions; and forming crystal layers containing the activated impurities and forming nickel silicide films on the crystal layers at low temperature by radiating microwaves to the amorphous regions and the nickel films.
    Type: Application
    Filed: March 8, 2012
    Publication date: January 24, 2013
    Inventors: Tomonori Aoyama, Kiyotaka Miyano, Hiroshi Nakazawa
  • Publication number: 20120273790
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming an amorphous semiconductor film on a substrate. The method further includes annealing the amorphous semiconductor film by irradiating the substrate with a microwave to form a polycrystalline semiconductor film from the amorphous semiconductor film. The method further includes forming a transistor whose channel is the polycrystalline semiconductor film.
    Type: Application
    Filed: March 8, 2012
    Publication date: November 1, 2012
    Inventors: Tomonori AOYAMA, Kiyotaka MIYANO
  • Publication number: 20120225498
    Abstract: According to one embodiment, a manufacturing method of semiconductor device includes forming plural elements on a substrate, forming a silicon compound film so as to bury between a plurality of elements, and modifying the silicon compound film to a silicon dioxide film by radiating microwaves.
    Type: Application
    Filed: September 30, 2011
    Publication date: September 6, 2012
    Inventors: Tomonori Aoyama, Kiyotaka Miyano
  • Publication number: 20120181602
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion. The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.
    Type: Application
    Filed: January 10, 2012
    Publication date: July 19, 2012
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Masaru Kito, Kiyotaka Miyano, Shinji Mori, Ichiro Mizushima
  • Patent number: 8148717
    Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp (21541/T).
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
  • Patent number: 8124464
    Abstract: This disclosure concerns a semiconductor device comprising a convex-shaped semiconductor layer formed on a semiconductor substrate; an insulation film formed on the semiconductor substrate, the insulation film having a film thickness to the extent that a lower part of the semiconductor layer is buried; a gate electrode formed on a set of both opposed side faces via a gate insulation film; and a source region and a drain region formed on a side face side on which the gate electrode is not formed in the semiconductor layer, wherein the semiconductor layer is formed so as to dispose surfaces of a peripheral part excepting a central part on an outer side than surfaces of the central part covered by at least the gate electrode.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: February 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kiyotaka Miyano
  • Publication number: 20120025200
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.
    Type: Application
    Filed: January 31, 2011
    Publication date: February 2, 2012
    Inventors: Tomonori Aoyama, Kiyotaka Miyano, Yusuke Oshiki
  • Patent number: 8093141
    Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming an amorphous layer on a portion of a first silicon substrate having a first plane orientation, and irradiating with micro wave on the amorphous layer to transform from the amorphous layer into a crystalline layer having the first plane orientation.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: January 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Kiyotaka Miyano
  • Publication number: 20110215333
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.
    Type: Application
    Filed: September 16, 2010
    Publication date: September 8, 2011
    Inventors: Tomonori AOYAMA, Yusuke Oshiki, Kiyotaka Miyano
  • Publication number: 20110159634
    Abstract: In one embodiment, a method of manufacturing a back side illuminated imaging device includes forming a semiconductor detection device and a peripheral circuit device on a semiconductor substrate, and bonding the semiconductor substrate onto a holding substrate via the semiconductor detection device and the peripheral circuit device. The method further includes removing the semiconductor substrate from the holding substrate to transfer the semiconductor detection device and the peripheral circuit device onto the holding substrate. The method further includes forming an amorphous semiconductor layer in which impurities are introduced, on the semiconductor detection device transferred onto the holding substrate, and annealing the amorphous semiconductor layer by using a microwave.
    Type: Application
    Filed: September 21, 2010
    Publication date: June 30, 2011
    Inventors: Yusuke Oshiki, Kiyotaka Miyano
  • Publication number: 20110127578
    Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp (21541/T).
    Type: Application
    Filed: January 28, 2011
    Publication date: June 2, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
  • Patent number: 7947610
    Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: May 24, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Seiji Inumiya, Yasumasa Suizu, Yoshio Ozawa, Kiyotaka Miyano, Masayuki Tanaka
  • Publication number: 20110111580
    Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming an amorphous layer on a portion of a first silicon substrate having a first plane orientation, and irradiating with micro wave on the amorphous layer to transform from the amorphous layer into a crystalline layer having the first plane orientation.
    Type: Application
    Filed: September 9, 2010
    Publication date: May 12, 2011
    Inventors: Tomonori AOYAMA, Kiyotaka Miyano