Patents by Inventor Klaus Reingruber

Klaus Reingruber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220108976
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Application
    Filed: December 16, 2021
    Publication date: April 7, 2022
    Inventors: Georg SEIDEMANN, Klaus REINGRUBER, Christian GEISSLER, Sven ALBERS, Andreas WOLTER, Marc DITTES, Richard PATTEN
  • Patent number: 11239199
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten
  • Patent number: 10937932
    Abstract: An optoelectronic component includes a carrier, an optoelectronic arrangement, and a potting material, wherein the optoelectronic arrangement includes an optoelectronic semiconductor chip, the optoelectronic arrangement is arranged above a top side of the carrier, the potting material is arranged above the top side of the carrier such that the optoelectronic arrangement is embedded into the potting material, a radiation emission face of the optoelectronic arrangement is not covered by the potting material, and a surface of the potting material is formed above the radiation emission face in relation to the top side of the carrier.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 2, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Peter Nagel, Klaus Reingruber, Simone Brantl, Konrad Wagner, Ralf Müller
  • Patent number: 10854590
    Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: December 1, 2020
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Klaus Reingruber, Richard Patten, Georg Seidemann, Christian Geissler
  • Publication number: 20200373470
    Abstract: In at least one embodiment, the optoelectronic component comprises an optoelectronic semiconductor chip with an emission side and a rear side opposite the emission side. Furthermore, the component comprises a housing body with a top side and an underside opposite the top side, and a metal layer on the top side of the housing body. During proper operation, the semiconductor chip emits primary electromagnetic radiation via the emission side. The semiconductor chip is embedded in the housing body and laterally surrounded by the housing body. The emission side is on the rear side and the top side is downstream of the underside along a main emission direction of the semiconductor chip. The metal layer is at least partially reflecting or absorbing radiation generated by the optoelectronic component.
    Type: Application
    Filed: March 12, 2019
    Publication date: November 26, 2020
    Inventors: Klaus REINGRUBER, Michael ZITZLSPERGER, Matthias GOLDBACH
  • Patent number: 10816742
    Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 27, 2020
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Christian Geissler, Sven Albers, Thomas Wagner, Marc Dittes, Klaus Reingruber, Andreas Wolter, Richard Patten
  • Publication number: 20200273832
    Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Sven ALBERS, Klaus REINGRUBER, Georg SEIDEMANN, Christian GEISSLER, Richard PATTEN
  • Patent number: 10741486
    Abstract: Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.
    Type: Grant
    Filed: March 6, 2016
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Klaus Reingruber, Sven Albers, Christian Geissler
  • Patent number: 10714455
    Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Klaus Reingruber
  • Publication number: 20200212271
    Abstract: A method for producing optoelectronic semiconductor components may include applying optoelectronic semiconductor chips for generating radiation to a carrier, producing a potting around the semiconductor chips with a potting top side facing away from the carrier such that the semiconductor chips remain free of a reflective potting material. The potting has trenches between the semiconductor chips, and the trenches are arranged at a distance from the semiconductor chips; the trenches do not touch the semiconductor chips. The method may further include filling the trenches with a supporting material to form at least one supporting body and leaving the potting alongside the trenches free of the supporting material.
    Type: Application
    Filed: July 18, 2018
    Publication date: July 2, 2020
    Inventors: Klaus Reingruber, Andreas Reith, Tobias Gebuhr
  • Patent number: 10680147
    Abstract: A method of producing a lighting device includes a radiation-emitting optoelectronic component, including: arranging the component on a carrier, applying a first layer on the carrier, wherein the first layer surrounds the component at least laterally in the form of a circumferential frame, and subsequently applying a second layer on the first layer laterally next to the frame, wherein the second layer includes a greater hardness than the first layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 9, 2020
    Assignee: OSRAM Oled GmbH
    Inventors: Peter Nagel, Klaus Reingruber
  • Publication number: 20200176436
    Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 4, 2020
    Inventors: Sven ALBERS, Klaus REINGRUBER, Richard PATTEN, Georg SEIDEMANN, Christian GEISSLER
  • Patent number: 10672731
    Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Klaus Reingruber, Georg Seidemann, Christian Geissler, Richard Patten
  • Patent number: 10651102
    Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 12, 2020
    Assignee: Intel IP Corporation
    Inventors: Klaus Reingruber, Christian Geissler, Georg Seidemann, Sonja Koller
  • Publication number: 20200066692
    Abstract: Package devices (systems and methods for their manufacture) may have an integrated circuit (IC) chip mounted on a top surface of a package substrate of and IC package, and embedded in a mold compound formed onto the top surface. They may also have conductive elements mounted on the top surface of the package substrate, embedded in the mold compound, horizontally disposed at a first vertical sidewall of the package device, and having vertical contact pads exposed at the first vertical sidewall. Conductor material traces of the IC package may electrically couple contacts of the chip to the conductive elements. Traces of the IC package may also electrically couple contacts of the chip to bottom surface contacts of the IC package. The vertical contact pads provide a shorter signal path to another device having vertically mounted surface contacts or opposing contact pads, thus improving signaling to the other device.
    Type: Application
    Filed: December 14, 2016
    Publication date: February 27, 2020
    Applicant: Intel IP Corporation
    Inventors: Andreas WOLTER, Bernd WAIDHAS, Georg SEIDEMANN, Klaus REINGRUBER, Thomas WAGNER
  • Publication number: 20200068711
    Abstract: Systems and methods are provide to form one or more pads on at least one surface associated with a portion of a component, for example, a component associated with a surface-mounted device (SMD). Further, the systems and methods are directed to providing metal (for example, copper, Cu) layers on the surface of one or more terminations (for example, solder termination pads) of an electrical component. In one embodiment, the metal layers include metal termination pads that are fabricated on a carrier layer; components can be soldered to these termination pads, then the components with the metal pads can be debonded from the carrier layer. As such, the solder terminations of the components can be covered by the metal pads. The disclosed systems and methods can permit or otherwise facilitate a wider selection and easy availability of the components to be electrically and/or mechanically connected to semiconductor packages.
    Type: Application
    Filed: November 23, 2016
    Publication date: February 27, 2020
    Inventors: Andreas Wolter, Georg Seidemann, Klaus Reingruber, Thomas Wagner
  • Patent number: 10522485
    Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 31, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Publication number: 20190393191
    Abstract: Embodiments may include an IC having an active substrate containing devices, and a bulk substrate, separated by an oxide layer or an etching stop layer. The IC may be partially thinned from a backside of the bulk substrate to create a cavity, while maintaining the dicing streets and/or the edges of the bulk substrate without being thinned. The cavity may be surrounded by a first edge and a second edge of the bulk substrate. An additional IC may be placed within the cavity of the bulk substrate to form a stacking IC with a reduced height. The ICs of the stacking IC may be electronically coupled using TSVs embedded within the active substrate of the ICs. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 27, 2016
    Publication date: December 26, 2019
    Inventors: Klaus REINGRUBER, Georg SEIDEMANN, Andreas WOLTER, Bernd WAIDHAS, Thomas WAGNER
  • Patent number: 10490527
    Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Publication number: 20190333886
    Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Inventors: Klaus Reingruber, Andreas Wolter, Georg Seidemann, Thomas Wagner, Bernd Waidhas