Patents by Inventor Klaus Reingruber
Klaus Reingruber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955462Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.Type: GrantFiled: December 16, 2021Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Georg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten
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Patent number: 11715820Abstract: In at least one embodiment, the optoelectronic component comprises an optoelectronic semiconductor chip with an emission side and a rear side opposite the emission side. Furthermore, the component comprises a housing body with a top side and an underside opposite the top side, and a metal layer on the top side of the housing body. During proper operation, the semiconductor chip emits primary electromagnetic radiation via the emission side. The semiconductor chip is embedded in the housing body and laterally surrounded by the housing body. The emission side is on the rear side and the top side is downstream of the underside along a main emission direction of the semiconductor chip. The metal layer is at least partially reflecting or absorbing radiation generated by the optoelectronic component.Type: GrantFiled: March 12, 2019Date of Patent: August 1, 2023Assignee: OSRAM OLED GmbHInventors: Klaus Reingruber, Michael Zitzlsperger, Matthias Goldbach
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Patent number: 11670745Abstract: A method for producing optoelectronic semiconductor components may include applying optoelectronic semiconductor chips for generating radiation to a carrier, producing a potting around the semiconductor chips with a potting top side facing away from the carrier such that the semiconductor chips remain free of a reflective potting material. The potting has trenches between the semiconductor chips, and the trenches are arranged at a distance from the semiconductor chips; the trenches do not touch the semiconductor chips. The method may further include filling the trenches with a supporting material to form at least one supporting body and leaving the potting alongside the trenches free of the supporting material.Type: GrantFiled: July 18, 2018Date of Patent: June 6, 2023Assignee: Osram OLED GmbHInventors: Klaus Reingruber, Andreas Reith, Tobias Gebuhr
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Patent number: 11469213Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.Type: GrantFiled: September 28, 2016Date of Patent: October 11, 2022Assignee: Intel CorporationInventors: Georg Seidemann, Thomas Wagner, Klaus Reingruber, Bernd Waidhas, Andreas Wolter
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Patent number: 11424209Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.Type: GrantFiled: May 11, 2020Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Sven Albers, Klaus Reingruber, Georg Seidemann, Christian Geissler, Richard Patten
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Publication number: 20220108976Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.Type: ApplicationFiled: December 16, 2021Publication date: April 7, 2022Inventors: Georg SEIDEMANN, Klaus REINGRUBER, Christian GEISSLER, Sven ALBERS, Andreas WOLTER, Marc DITTES, Richard PATTEN
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Patent number: 11239199Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.Type: GrantFiled: December 26, 2015Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Georg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten
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Patent number: 10937932Abstract: An optoelectronic component includes a carrier, an optoelectronic arrangement, and a potting material, wherein the optoelectronic arrangement includes an optoelectronic semiconductor chip, the optoelectronic arrangement is arranged above a top side of the carrier, the potting material is arranged above the top side of the carrier such that the optoelectronic arrangement is embedded into the potting material, a radiation emission face of the optoelectronic arrangement is not covered by the potting material, and a surface of the potting material is formed above the radiation emission face in relation to the top side of the carrier.Type: GrantFiled: February 26, 2019Date of Patent: March 2, 2021Assignee: OSRAM OLED GmbHInventors: Peter Nagel, Klaus Reingruber, Simone Brantl, Konrad Wagner, Ralf Müller
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Patent number: 10854590Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.Type: GrantFiled: December 23, 2015Date of Patent: December 1, 2020Assignee: Intel IP CorporationInventors: Sven Albers, Klaus Reingruber, Richard Patten, Georg Seidemann, Christian Geissler
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Publication number: 20200373470Abstract: In at least one embodiment, the optoelectronic component comprises an optoelectronic semiconductor chip with an emission side and a rear side opposite the emission side. Furthermore, the component comprises a housing body with a top side and an underside opposite the top side, and a metal layer on the top side of the housing body. During proper operation, the semiconductor chip emits primary electromagnetic radiation via the emission side. The semiconductor chip is embedded in the housing body and laterally surrounded by the housing body. The emission side is on the rear side and the top side is downstream of the underside along a main emission direction of the semiconductor chip. The metal layer is at least partially reflecting or absorbing radiation generated by the optoelectronic component.Type: ApplicationFiled: March 12, 2019Publication date: November 26, 2020Inventors: Klaus REINGRUBER, Michael ZITZLSPERGER, Matthias GOLDBACH
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Patent number: 10816742Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.Type: GrantFiled: November 6, 2018Date of Patent: October 27, 2020Assignee: Intel IP CorporationInventors: Georg Seidemann, Christian Geissler, Sven Albers, Thomas Wagner, Marc Dittes, Klaus Reingruber, Andreas Wolter, Richard Patten
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Publication number: 20200273832Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.Type: ApplicationFiled: May 11, 2020Publication date: August 27, 2020Inventors: Sven ALBERS, Klaus REINGRUBER, Georg SEIDEMANN, Christian GEISSLER, Richard PATTEN
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Patent number: 10741486Abstract: Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.Type: GrantFiled: March 6, 2016Date of Patent: August 11, 2020Assignee: Intel CorporationInventors: Klaus Reingruber, Sven Albers, Christian Geissler
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Patent number: 10714455Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.Type: GrantFiled: December 10, 2018Date of Patent: July 14, 2020Assignee: Intel IP CorporationInventors: Georg Seidemann, Klaus Reingruber
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Publication number: 20200212271Abstract: A method for producing optoelectronic semiconductor components may include applying optoelectronic semiconductor chips for generating radiation to a carrier, producing a potting around the semiconductor chips with a potting top side facing away from the carrier such that the semiconductor chips remain free of a reflective potting material. The potting has trenches between the semiconductor chips, and the trenches are arranged at a distance from the semiconductor chips; the trenches do not touch the semiconductor chips. The method may further include filling the trenches with a supporting material to form at least one supporting body and leaving the potting alongside the trenches free of the supporting material.Type: ApplicationFiled: July 18, 2018Publication date: July 2, 2020Inventors: Klaus Reingruber, Andreas Reith, Tobias Gebuhr
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Patent number: 10680147Abstract: A method of producing a lighting device includes a radiation-emitting optoelectronic component, including: arranging the component on a carrier, applying a first layer on the carrier, wherein the first layer surrounds the component at least laterally in the form of a circumferential frame, and subsequently applying a second layer on the first layer laterally next to the frame, wherein the second layer includes a greater hardness than the first layer.Type: GrantFiled: November 16, 2018Date of Patent: June 9, 2020Assignee: OSRAM Oled GmbHInventors: Peter Nagel, Klaus Reingruber
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Publication number: 20200176436Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.Type: ApplicationFiled: December 23, 2015Publication date: June 4, 2020Inventors: Sven ALBERS, Klaus REINGRUBER, Richard PATTEN, Georg SEIDEMANN, Christian GEISSLER
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Patent number: 10672731Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.Type: GrantFiled: December 23, 2015Date of Patent: June 2, 2020Assignee: Intel IP CorporationInventors: Sven Albers, Klaus Reingruber, Georg Seidemann, Christian Geissler, Richard Patten
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Patent number: 10651102Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.Type: GrantFiled: December 18, 2015Date of Patent: May 12, 2020Assignee: Intel IP CorporationInventors: Klaus Reingruber, Christian Geissler, Georg Seidemann, Sonja Koller
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Publication number: 20200066692Abstract: Package devices (systems and methods for their manufacture) may have an integrated circuit (IC) chip mounted on a top surface of a package substrate of and IC package, and embedded in a mold compound formed onto the top surface. They may also have conductive elements mounted on the top surface of the package substrate, embedded in the mold compound, horizontally disposed at a first vertical sidewall of the package device, and having vertical contact pads exposed at the first vertical sidewall. Conductor material traces of the IC package may electrically couple contacts of the chip to the conductive elements. Traces of the IC package may also electrically couple contacts of the chip to bottom surface contacts of the IC package. The vertical contact pads provide a shorter signal path to another device having vertically mounted surface contacts or opposing contact pads, thus improving signaling to the other device.Type: ApplicationFiled: December 14, 2016Publication date: February 27, 2020Applicant: Intel IP CorporationInventors: Andreas WOLTER, Bernd WAIDHAS, Georg SEIDEMANN, Klaus REINGRUBER, Thomas WAGNER