Patents by Inventor Klaus Reingruber
Klaus Reingruber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180374819Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.Type: ApplicationFiled: December 18, 2015Publication date: December 27, 2018Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
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Publication number: 20180358317Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.Type: ApplicationFiled: December 23, 2015Publication date: December 13, 2018Inventors: Sven ALBERS, Klaus REINGRUBER, Georg SEIDEMANN, Christian GEISSLER, Richard PATTEN
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Publication number: 20180342431Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.Type: ApplicationFiled: December 18, 2015Publication date: November 29, 2018Inventors: Klaus Reingruber, Christian Geissler, Georg Seidemann, Sonja Koller
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Publication number: 20180331070Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.Type: ApplicationFiled: December 26, 2015Publication date: November 15, 2018Applicant: Intel IP CorporationInventors: Georg SEIDEMANN, Klaus REINGRUBER, Christian GEISSLER, Sven ALBERS, Andreas WOLTER, Marc DITTES, Richard PATTEN
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Publication number: 20180331053Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.Type: ApplicationFiled: December 21, 2015Publication date: November 15, 2018Inventors: Christian GEISSLER, Sven ALBERS, Georg SEIDEMANN, Andreas WOLTER, Klaus REINGRUBER, Thomas WAGNER, Marc DITTES
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Publication number: 20180331080Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.Type: ApplicationFiled: December 21, 2015Publication date: November 15, 2018Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
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Patent number: 10121726Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.Type: GrantFiled: August 28, 2015Date of Patent: November 6, 2018Assignee: INTEL IP CORPORATIONInventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Alexandra Atzesdorfer, Sonja Koller
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Publication number: 20180226185Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.Type: ApplicationFiled: January 4, 2018Publication date: August 9, 2018Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter
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Publication number: 20180204831Abstract: An apparatus including an electrostatic discharge circuit including a first circuit portion coupled beneath a die contact pad of an integrated circuit die and a second circuit portion in an interposer separate from the integrated circuit die, the interposer including a first contact point coupled to the contact pad of the integrated circuit die and a second contact point operable for connection to an external source. A method including forming an integrated circuit die including a first electrostatic discharge structure beneath a contact pad of the die; and coupling the die to an interposer including an interposer contact and a second electrostatic discharge structure, wherein a signal at the contact pad of the die is operable to be routed through the interposer.Type: ApplicationFiled: September 14, 2015Publication date: July 19, 2018Inventors: Georg SEIDEMANN, Christian GEISSLER, Klaus REINGRUBER
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Publication number: 20180150156Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.Type: ApplicationFiled: January 25, 2018Publication date: May 31, 2018Inventors: Sven Albers, Klaus Reingruber, Teodora Ossiander, Andreas Wolter, Sonja Koller, Georg Seidemann, Jan Proschwitz, Hans-Joachim Barth, Bastiaan Elshof
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Publication number: 20180095426Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Thorsten Meyer, Gerald Ofner
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Publication number: 20180096970Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Klaus Reingruber, Andreas Wolter, Georg Seidemann, Thomas Wagner, Bernd Waidhas
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Publication number: 20180092443Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Thorsten Meyer, Gerald Ofner
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Patent number: 9921694Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.Type: GrantFiled: December 16, 2014Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Sven Albers, Klaus Reingruber, Teodora Ossiander, Andreas Wolter, Sonja Koller, Georg Seidemann, Jan Proschwitz, Hans-Joachim Barth, Bastiaan Elshof
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Publication number: 20180068939Abstract: Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a patterned metal redistribution layer (RDL) may be coupled with the second face of the dielectric layer. The line may include a first portion with a first width and a second portion directly coupled to the first portion, the second portion having a second width. The first portion may extend beyond a plane of the second face of the dielectric layer, and the second portion may be positioned between the first face and the second face of the dielectric layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 15, 2017Publication date: March 8, 2018Inventors: Klaus Reingruber, Sven Albers, Christian Geissler
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Patent number: 9865387Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.Type: GrantFiled: December 2, 2015Date of Patent: January 9, 2018Assignee: Intel IP CorporationInventors: Sven Albers, Klaus Reingruber, Andreas Wolter
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Publication number: 20180005991Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Georg Seidemann, Klaus Reingruber
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Publication number: 20170285280Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.Type: ApplicationFiled: April 2, 2016Publication date: October 5, 2017Inventors: Georg Seidemann, Christian Geissler, Sven Albers, Thomas Wagner, Marc Dittes, Klaus Reingruber, Andreas Wolter, Richard Patten
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Publication number: 20170284636Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Applicant: Intel IP CorporationInventors: Marc Stephan Dittes, Sven Albers, Christian Georg Geissler, Andreas Wolter, Klaus Reingruber, Georg Seidemann, Thomas Wagner, Richard Patten
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Publication number: 20170278778Abstract: An interconnect adaptor may be fabricated having a substantially planar surface, to which a microelectronic package may be electrically attached, and a non-planar surface with at least one interconnect extending from the interconnect adaptor planar surface to the interconnect adaptor non-planar surface. The interconnect adaptor non-planar surface may be shaped to substantially conform to a shape of a microelectronic substrate to which it may be attached, which eliminates the need to bend or otherwise adapt the microelectronic package to conform to the microelectronic substrate.Type: ApplicationFiled: June 14, 2017Publication date: September 28, 2017Applicant: INTEL CORPORATIONInventors: Christian Geissler, Klaus Reingruber, Sven Albers