Patents by Inventor Koichi Hashimoto

Koichi Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6332873
    Abstract: A massaging apparatus including a head unit, a pair of housings and a pair of arms. The head unit is configured to massage a body of a user. The pair of housings are connected to opposite sides of the head unit respectively and extend in opposite directions from the head unit. The pair of arms are configured to be held by the user and provided to the pair of housings respectively. The pair of arms are flexible.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: December 25, 2001
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Haruhiko Naruse, Koichi Hashimoto
  • Patent number: 6300655
    Abstract: A plurality of memory cell transistors are formed on a principal surface of a semiconductor substrate in a plurality of active regions defined by an isolation region. Each memory cell transistor uses one word line as its gate electrode and has a pair of source and drain regions defined by the gate electrode and the isolation region. One of a pair of source and drain regions is connected to one of a plurality of bit lines, and the other region is connected to one of a plurality of capacitors. Three sides of the other region are defined by the isolation region. The other region includes a first impurity doped region extending to under another word line adjacent to the one word line and a second impurity doped region partially overlapping the first impurity doped region and the gate electrode.
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: October 9, 2001
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Koichi Hashimoto
  • Patent number: 6291064
    Abstract: A fiber reinforced thermoplastic resin molded product having a good surface appearance; fiber reinforced thermoplastic resin pellets useful for making fiber reinforced thermoplastic resin molded products; and processes for making fiber reinforced thermoplastic resin molded products and processes for producing fiber reinforced thermoplastic resin pellets.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: September 18, 2001
    Assignee: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel Ltd).
    Inventors: Ryosaku Kadowaki, Koichi Hashimoto, Toshihiro Asai, Toshiaki Okumura
  • Patent number: 6285045
    Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fi
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: September 4, 2001
    Assignee: Fujitsu Limited
    Inventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo
  • Patent number: 6251721
    Abstract: After an SAC film is formed to a thickness not to fill the spaces between gate electrodes in a memory cell region, a silicon oxide film is formed to a thickness to fill the spaces. A side wall made of a silicon oxide film is formed on the side surface of only a gate electrode in a peripheral circuit region, and a metal silicide is formed on the exposed substrate surface. A BLC film is formed on the entire surface. A contact hole is formed in self alignment using the SAC film and the BLC film. In this method, silicidation of the source/drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC can be simultaneously used to enable an increase in the degree of integration and improvement of performance of a semiconductor device having a metal silicide on the transistor in the logic circuit.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: June 26, 2001
    Assignee: Fujitsu Limited
    Inventors: Kenichi Kanazawa, Koichi Hashimoto, Yoshihiro Takao, Masaki Katsube
  • Patent number: 6167154
    Abstract: When an original wherein a plurality of binary image areas in different density or the like coexist is printed by stencil making, tone characteristics of a tone image area are preserved and blur or extinction of a faint letter, or smear of a letter written on a dark background in a binary image area is prevented from occurring and print without incongruity due to density different is obtained.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: December 26, 2000
    Assignee: RISO Laboratory, Inc.
    Inventors: Miel Renaud, Koichi Hashimoto
  • Patent number: 6160294
    Abstract: A semiconductor device of the present invention includes an insulating layer covering a plurality of semiconductor elements formed in a semiconductor layer, an opening portion formed in the insulating layer respective conductive portions of the plurality of semiconductor elements in the insulating layer, and a conductive pattern formed in the opening portion for connecting respective conductive portions of the plurality of semiconductor elements.
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: December 12, 2000
    Assignee: Fujitsu Limited
    Inventor: Koichi Hashimoto
  • Patent number: 6157068
    Abstract: A first metal silicide film is formed on an exposed silicon region of a substrate on which the silicon region and an insulating region are exposed. A metal film is deposited over the whole surface of the substrate covering the first metal silicide film, the metal film capable of being silicidized. A silicon film is deposited on the surface of the metal film. The silicon film and metal film are patterned to form a lamination pattern of the silicon film and metal film continuously extending from a partial area of the exposed silicon region to a partial area of the insulating region. The lamination pattern is heated to establish a silicidation reaction and form a second metal silicide layer.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Koichi Hashimoto, Hiromi Hayashi
  • Patent number: 6154575
    Abstract: In an image thickening processing method, a thickening processing is carried out on a binary image made up of black picture elements and white picture elements, which are adjacent to one another along vertical and horizontal directions. Each of the black picture elements is set as a black picture element of interest. A vertically adjacent picture element, which is adjacent to the black picture element of interest along a single vertical direction, and a horizontally adjacent picture element, which is adjacent to the black picture element of interest along a single horizontal direction, are detected. Also, an obliquely adjacent picture element, which is adjacent to all of the black picture element of interest, the vertically adjacent picture element, and the horizontally adjacent picture element, is detected.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: November 28, 2000
    Assignee: Riso Kagaku Corporation
    Inventor: Koichi Hashimoto
  • Patent number: 6130482
    Abstract: The present invention relates to a metallization technique of a semiconductor device, more specifically to a semiconductor device having a wiring or plug of a suitable structure for high integration and a method for fabrication of the semiconductor device. The semiconductor device comprises a base substrate 10; an inter-layer insulation film 20 including a first insulation film 16 formed on the base substrate and a second insulation film 18 formed on the base substrate, and having a contact hole 22 which reaches the base substrate 10; and a conducting film 24 formed on an inside wall and a bottom of the contact hole 22, a width of the contact hole in the first insulation film 16 being larger than a width of the contact hole 22 in the second insulation film 18. The conducting film 24 on the inside wall of the contact hole 22, and the conducting film 24 on the bottom of the contact hole 22 is uninterrupted on a boundary.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: October 10, 2000
    Assignee: Fujitsu Limited
    Inventors: Hiroki Iio, Koichi Hashimoto, Wataru Futo
  • Patent number: 6126772
    Abstract: An object is to peel off a disused resist from an article, e.g., a silicon wafer, with an adhesive sheet while preventing impurities contained in the adhesive sheet from transferring to the surface of the article, e.g., wafer, and from thus arousing electrical troubles resulting in problems such as decreases in the yield and reliability of the article. A method for resist removal comprising forming an adhesive layer on an article on which a resist is present and peeling the adhesive layer as a united sheet including the resist material from the article, characterized in that the adhesive layer has been regulated so as to have a modulus of elasticity of 1 Kg/mm.sup.2 or higher in the peeling, and an adhesive or an adhesive sheet both for use in the method.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: October 3, 2000
    Assignee: Nitto Denko Corporation
    Inventors: Takayuki Yamamoto, Tatsuya Kubozono, Yasuo Kihara, Yuji Okawa, Koichi Hashimoto, Takeshi Matsumura, Tatsuya Sekido, Masayuki Yamamoto, Chiaki Harada
  • Patent number: 6086701
    Abstract: In accordance with the production process according to the present invention, a stamper having a desired pattern for the formation of a disc board can be produced without worsening the working atmosphere or causing any other problems. A novel process for the production of a stamper for the formation of a disc board is provided, which comprises applying an adhesive tape to the surface of a stamper body on which an unnecessary resist remains, and then peeling the adhesive tape off the stamper body so that the unnecessary resist is transferred to the adhesive tape to remove itself from the stamper body.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: July 11, 2000
    Assignee: Nitto Denko Corporation
    Inventors: Makoto Namikawa, Koichi Hashimoto, Haruo Ioka, Yukari Konda
  • Patent number: 6026010
    Abstract: A semiconductor memory device includes a plurality of memory cells located at intersections of the word lines and the bit lines, each of the memory cells having a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of the transfer transistor being connected to a word line, the source of the transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor. A memory cell pair is formed by two nearby memory cells and these two memory cells of the memory cell pair have a common bit line contact area. In a unit region defined by word line Nos. "i" and "i+1" and bit line Nos. "j" and "j+4", there are provided bit line contact areas and storage capacitor contact areas with a ratio of 1:2 between the number of the bit line contact areas and the storage capacitor contact areas.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: February 15, 2000
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Koichi Hashimoto
  • Patent number: 6007732
    Abstract: A pattern forming method having a step of forming an amorphous carbon film on a patterning layer formed on a substrate, a step of forming a photoresist film on the amorphous carbon film, a step of selectively exposing and developing the photoresist film to form a photoresist pattern, and a step of successively dry-etching the amorphous carbon film and the patterning layer by using the photoresist film as an etching mask. Desired optical constants of an amorphous carbon film formed by sputtering can be obtained by controlling a substrate temperature and other parameters.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: December 28, 1999
    Assignee: Fujitsu Limited
    Inventors: Koichi Hashimoto, Toshiyuki Ohtsuka, Fumihiko Shinpuku, Daisuke Matsunaga, Takayuki Enda
  • Patent number: 5978554
    Abstract: An image processing method for determining a characteristic of image data in each area in whole image area and performing binarization processing appropriate for the characteristic, the method comprises the steps of: calculating gradation levels around a pixel in the image data; selecting a threshold value matrix appropriate for the pixel, in response to the calculating step, from the group consisting of a threshold value matrix consisting of single threshold value elements for simple binarization, a threshold value matrix comprising different threshold value elements for halftone processing, and at least one threshold value matrix comprising interpolation of both the threshold value matrixes; and binarizing the pixel by a systematic dither method using the threshold value matrix which is selected in the selecting step.
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: November 2, 1999
    Assignee: Riso Kagaru Corporation
    Inventors: Junichi Hakamada, Koichi Hashimoto
  • Patent number: 5967934
    Abstract: A planetary transmission has a plurality of axially arranged planetary gear units each including sun gears, planet gears in mesh with the sun gears, and ring gears coaxial with the sun gears and in mesh with the planet gears, the arrangement being such that one of the ring gears in each planetary gear unit is blocked from being rotated while the other ring gear is made rotatable for allowing an output to be taken out, upon which the ring gear of which rotation is blocked is made selectable for changing over the reduction ratio, and a smooth bilateral change-over of speed change can be realized by executing the change-over between rotation-blocked and rotation-free states of the ring gear by means of a one-way clutch capable of releasing the rotation blocking.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: October 19, 1999
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Yosuke Ishida, Koichi Hashimoto, Hidenori Shimizu
  • Patent number: 5932901
    Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fi
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: August 3, 1999
    Assignee: Fujitsu Limited
    Inventors: Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Kenichi Inoue, Koichi Hashimoto, Wataru Futo
  • Patent number: 5931905
    Abstract: TV mail system comprising a plurality of televisions each having a receiving function capable of receiving broadcasting radio waves and displaying a program, and a mail server to which the televisions are connected through communication lines, wherein the television has a mail sending function for making mail including at least destination information and the body of a mail to output the mail data to the mail server and a mail receiving function for displaying the contents of mail data received from the mail server together with the received mail, the mail server has a database in which authentication information of users are registered, a receiving mail box for storing received mail data, mail boxes for receivers, a mail distribution device for distributing, to a mail box for the receiver, mail data stored in the receiving mail box by making a reference to the authentication database and an outputting device which sends out the mail data received from one television to at least one different television in co
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Hashimoto, Isamu Miura, Yasuko Katayama
  • Patent number: 5913139
    Abstract: A first metal silicide film is formed on an exposed silicon region of a substrate on which the silicon region and an insulating region are exposed. A metal film is deposited over the whole surface of the substrate covering the first metal silicide film, the metal film capable of being silicidized. A silicon film is deposited on the surface of the metal film. The silicon film and metal film are patterned to form a lamination pattern of the silicon film and metal film continuously extending from a partial area of the exposed silicon region to a partial area of the insulating region. The lamination pattern is heated to establish a silicidation reaction and form a second metal silicide layer.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: June 15, 1999
    Assignee: Fujitsu Limited
    Inventors: Koichi Hashimoto, Hiromi Hayashi
  • Patent number: 5870656
    Abstract: An image forming apparatus having an image bearing member for bearing an electrostatic image to be developed by toner, a transfer device for transferring a toner image formed on the image bearing member onto a transfer material, and developing and cleaning device for developing the electrostatic image with developer including toner and carrier and for cleaning residual toner remaining on the image bearing member after transferring, the developing and cleaning device having a developer bearing member for bearing the developer and serving to effect development and cleaning by causing a magnet brush formed by the carrier to contact with the image bearing member, and wherein the following relation is satisfied:.vertline.V.sub.s1 V.sub.dr .vertline./.vertline.V.sub.dr .vertline..times.L.times.m.times..alpha..gtoreq.7(where, V.sub.s1 is a moving speed (mm/sec.) of a surface of the developer bearing member, V.sub.dr is a moving speed (mm/sec.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: February 9, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaru Hibino, Yoshiaki Kobayashi, Koichi Hashimoto, Ichiro Ozawa