Semiconductor device with self-aligned contact and its manufacture
A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.
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Claims
1. A semiconductor device having a memory cell area and a peripheral circuit area on a semiconductor substrate, comprising:
- a transfer transistor in the memory cell area including a pair of impurity diffusion regions formed in said substrate and a gate electrode formed over a surface of said substrate between said pair of impurity diffusion regions;
- a first insulating film covering the upper and side surfaces of said gate electrode;
- a second insulating film formed on said substrate covering said first insulating film;
- a pair of contact holes formed through said second insulating film and reaching said pair of impurity diffusion regions;
- a conductive plug embedded in one of said contact holes and connected to one of said pair of impurity diffusion regions;
- a third insulating film formed on said second insulating film covering said conductive plug, and having a first aperture on the other of said pair of contact holes;
- a bit line formed on said third insulating film and connected to the other of said pair of impurity diffusion regions through said first aperture and the other of said pair of contact holes;
- a fourth insulating film covering the upper and side surfaces of said bit line;
- a second aperture formed through said third insulating film in alignment with the fourth insulating film covering the side surface of said bit line;
- a storage electrode formed to extend over said bit line, insulated from said bit line by said third and fourth insulating films, and electrically connected to said conductive plug through said second aperture;
- a dielectric film formed on a surface of said storage electrode; and
- an opposing electrode formed on a surface of said dielectric film.
2. A semiconductor device according to claim 1, wherein said second insulating film comprises a lower layer formed of a laminate of two or more insulating films having different etching characteristics and an upper layer formed on the lower layer.
3. A semiconductor device according to claim 2, wherein said laminate comprises an oxide layer and a nitride layer formed on the oxide layer.
4. A semiconductor device according to claim 2, wherein the upper layer of said second insulating film comprises a laminate of two or more insulating films of different etching characteristics.
5. A semiconductor device according to claim 4, wherein said laminate of the upper layer comprises a borophospho-silicate glass (BPSG) layer and a conformal layer formed on the BPSG layer.
6. A semiconductor device according to claim 5, wherein said conformal layer is a nitride layer.
7. A semiconductor device according to claim 5, wherein said conformal layer is a high temperature oxide film.
8. A semiconductor device according to claim 1, wherein said first insulating film comprises a lower layer covering the upper surface of said gate electrode, and an upper layer covering the side surface of said gate electrode.
9. A semiconductor device according to claim 8, wherein said lower layer of the first insulating film comprises a laminate of an oxide film and an oxynitride film, and said lower layer of the first insulating film comprises an oxide film.
10. A semiconductor device according to claim 1, wherein said fourth insulating film comprises a lower layer covering an upper surface of said bit line and an upper layer covering a side surface of said bit line.
11. A semiconductor device according to claim 10, wherein said lower layer of the fourth insulating film comprises a laminate of an oxide film and an oxynitride film, and said upper layer of the fourth insulating film comprises an oxide film.
12. A semiconductor device according to claim 1, wherein said second insulating film has a generally flat upper surface.
13. A semiconductor device according to claim 1, further comprising:
- another transistor in said peripheral circuit area, including another pair of impurity diffusion regions formed in said substrate and another gate electrode formed over a surface of said substrate between said another pair of impurity diffusion regions;
- said first insulating film covering the upper and side surfaces of said another gate electrode; and
- another contact hole formed through said second insulating film and reaching one of said another pair of impurity diffusion regions.
14. A semiconductor device according to claim 1, wherein a plurality of said bit lines are provided and the width of each said bit line and a gap between adjacent bit lines are smaller than a diameter of said one contact hole.
15. A semiconductor device according to claim 1, wherein said bit line comprises another conductive plug embedded in said the other contact hole, and a wiring layer formed on said third insulating film and said another conductive plug.
16. A semiconductor device according to claim 1, wherein said bit line comprises a conductive layer covering inner surfaces of said the other contact hole, and extends on said third insulating film.
17. A semiconductor device according to claim 1, further comprising:
- a fifth insulating film formed above said substrate covering said bit line and said fourth insulating film, and having a generally flat surface.
18. A semiconductor device according to claim 17, wherein said fifth insulating film comprises a lower layer formed of a laminate of two or more insulating films having different etching characteristics, and an upper layer formed on the lower layer.
19. A semiconductor device according to claim 18, wherein said laminate of said fifth insulating film comprises a conformal oxide film and a conformal nitride film.
20. A semiconductor device according to claim 18, wherein said fourth insulating film comprises a laminate of two or more insulating films having different etching characteristics, the laminate being formed on said bit line.
21. A semiconductor device having a memory cell area and a peripheral circuit area on a semiconductor substrate, comprising:
- a transfer transistor in the memory cell area including a pair of impurity diffusion regions formed in said substrate and a gate electrode formed over a surface of said substrate between said pair of impurity diffusion regions;
- a first insulating film formed on said substrate covering said transfer transistor;
- a first contact hole formed through said first insulating film and reaching one of said pair of impurity diffusion regions;
- a conductive plug embedded in said first contact hole;
- a second insulating film formed on said first insulating film covering said conductive plug;
- a second contact hole formed through said first and second insulating films and reaching the other of said pair of impurity diffusion regions;
- a bit line extending on said second insulating film and connected via said second contact hole to the other of said pair of impurity diffusion regions;
- a third insulating film covering an upper and a side surfaces of said bit line;
- an aperture formed through said second insulating film on said conductive plug, being aligned with the third insulating film covering the side surface of said bit line;
- a storage electrode electrically insulated from said bit line by said second and third insulating films, and electrically connected to said conductive plug through said aperture;
- a dielectric film formed on a surface of said storage electrode; and
- an opposing electrode formed on a surface of said dielectric film.
22. A semiconductor device according to claim 21, wherein said first insulating film has a generally flat upper surface.
23. A semiconductor device according to claim 21, wherein said bit line is made of a metal layer.
24. A semiconductor device according to claim 21, further comprising:
- another transistor formed in said peripheral circuit area including another pair of impurity diffusion regions formed in said substrate and another gate electrode formed over a surface of said substrate between said another pair of impurity diffusion regions;
- said first insulating film covering said another transistor;
- another contact hole formed through said first insulating film and reaching one of said another pair of impurity diffusion regions.
25. A semiconductor device comprising:
- a semiconductor substrate;
- a conductive layer disposed on said substrate;
- a first etching stopper film formed on said conductive layer;
- a first insulating film formed on said first etching stopper film;
- a second etching stopper film formed on said first insulating film; and
- a second insulating film formed on said second etching stopper film,
- wherein said second etching stopper film is thicker than said first etching stopper film, and said second insulating film is thicker than said first insulating film.
26. A semiconductor device according to claim 25, wherein said first insulating film has a generally flat surface.
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Type: Grant
Filed: Jul 10, 1997
Date of Patent: Aug 3, 1999
Assignee: Fujitsu Limited (Kawasaki)
Inventors: Kazuo Itabashi (Kawasaki), Osamu Tsuboi (Kawasaki), Yuji Yokoyama (Kawasaki), Kenichi Inoue (Kawasaki), Koichi Hashimoto (Kawasaki), Wataru Futo (Kawasaki)
Primary Examiner: Sheila V. Clark
Law Firm: Armstrong, Westerman, Hattori, McLeland & Naughton
Application Number: 8/890,991
International Classification: H01L 2710;
