Abstract: A semiconductor device comprises a semiconductor substrate having first conductivity type, a trench capacitor, provided in the substrate, having a charge accumulation region, a gate electrode provided on the substrate via a gate insulating film, a gate side wall insulating film provided on a side surface of the gate electrode, drain and source regions, provided in the substrate, having a second conductivity type, an isolation insulating film provided adjacent to the trench capacitor in the substrate to cover an upper surface of the charge accumulation region, a buried strap region having the second conductivity type, the buried strap region being provided to electrically connect an upper portion of the charge accumulation region to the source region in the substrate, and a pocket implantation region having the first conductivity type, the pocket implantation region being provided below the drain and source regions and being spaced apart from the strap region.

Abstract: A semiconductor device comprises an SOI substrate, a trench, a trench capacitor, and a conductive layer. The SOI substrate includes a fist semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor region formed on the buried insulating film. The trench is of a depth to reach the first semiconductor region, extending from a surface of the second semiconductor region on the SOI substrate and passing through the buried insulating film. The trench capacitor is formed within the trench. The conductive layer is formed in a region between a sidewall portion of the trench and the buried insulating film, and electrically connects the first semiconductor region and the second semiconductor region.

Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Abstract: A semiconductor device comprises an SOI substrate, a trench, a trench capacitor, and a conductive layer. The SOI substrate includes a fist semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor region formed on the buried insulating film. The trench is of a depth to reach the first semiconductor region, extending from a surface of the second semiconductor region on the SOI substrate and passing through the buried insulating film. The trench capacitor is formed within the trench. The conductive layer is formed in a region between a sidewall portion of the trench and the buried insulating film, and electrically connects the first semiconductor region and the second semiconductor region.

Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Abstract: This invention provides a semiconductor device by which a high-speed DRAM cell and logic circuit can be obtained without increasing the number of fabrication steps, and a method of fabricating the same. A memory cell is constructed of capacitors formed in two end portions of an element formation region of a silicon substrate and a MOS transistor formed between these capacitors. The interval between gate electrodes of MOS transistors in adjacent memory cells is made larger than the intervals between these gate electrodes and gate electrodes formed outside the former gate electrodes. A portion above an n-type diffusion layer connected to a capacitor node is filled with a spacer insulating film, and an n-type diffusion layer connected to a bit line is covered with the spacer insulating film. A titanium silicide film is formed on one of these n-type diffusion layers and the gate electrodes.

Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Abstract: The present invention is directed to a method of manufacture of a semiconductor device which is immune to short-channel effects including forming a first, second and third dielectric layers one conductivity type semiconductor substrate with the first dielectric layer forming a gate dielectric film on a surface of the one conductivity type semiconductor substrate, forming a groove in the second and third dielectric layer which exposes the first dielectric layer and forming a heavily doped region through the groove so that the width of the heavily doped region equals the width of the groove. The heavily doped region is of the same conductivity type as the semiconductor substrate.