Abstract: On a semiconductor substrate comprising a semiconductor device, a drift layer of a first conductivity type is formed, and a well layer of a second conductivity type in which an impurity concentration decreases toward the outside of the semiconductor substrate and a channel stopper layer of the first conductivity type are formed in the surface portion of the semiconductor substrate in the termination region. The termination region includes an alleviating region having the well layer formed therein, a RESURF region positioned outside the alleviating region and having the well layer formed shallowly, and a channel stopper region having the channel stopper layer formed therein. A gate wiring electrode is formed on the alleviating region and a channel stopper electrode is formed on the channel stopper region. The gate wiring electrode and the channel stopper electrode are covered with a semi-insulating film electrically connecting therebetween.

Abstract: A transistor and a diode are formed on a common semiconductor substrate, the semiconductor substrate includes a transistor region and a diode region, the diode region includes an n type first semiconductor layer provided on a second main surface side of the semiconductor substrate, an n type second semiconductor layer provided on the first semiconductor layer, a p type third semiconductor layer provided closer to a first main surface side of the semiconductor substrate than the second semiconductor layer, a first main electrode that applies a first potential to the diode, a second main electrode that applies a second potential to the diode, a plurality of diode trench gates that reach the second semiconductor layer from the first main surface of the semiconductor substrate, and a contact region provided in an upper layer portion of the third semiconductor layer, and the contact region is composed of a conductor material.

Abstract: A reservoir calculation device according to an embodiment includes a reservoir circuit and an output circuit. The reservoir circuit receives input data and outputs intermediate signals, each undergoing a transient change when the input data changes. The output circuit outputs an output signal obtained by combining the intermediate signals. The reservoir circuit includes intermediate circuits, each including a neuron circuit and an intermediate output circuit. The neuron circuit generates an intermediate voltage undergoing a transient change corresponding to weight data and the input data when the input data changes. The intermediate output circuit outputs an intermediate signal representing a level of the intermediate voltage from the neuron circuit. The neuron circuit includes a time constant circuit capable of changing a time constant. The time constant circuit is connected between a reference potential and an intermediate terminal outputting the intermediate voltage.

Abstract: An adjacent active trench in an IGBT region and an adjacent capacitance adjustment trench in a diode region are each provided in a stripe shape extending in a Y direction in a plan view. Each of a plurality of crossing trenches extends in an X direction orthogonal to the Y direction in a plan view and is provided in a stripe shape. Each of the plurality of crossing trenches is provided from the adjacent capacitance adjustment trench to the adjacent active trench in a plan view. Therefore, the gate electrode of the adjacent active trench and the capacitance adjustment electrode of the adjacent capacitance adjustment trench are electrically connected via the electrode for the crossing trench in the crossing trench.

Abstract: Provided is a semiconductor device that is easily controlled. The semiconductor device includes a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential, wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal, and the diode region includes a diode gate controlled by a diode gate signal.

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl

Abstract: A semiconductor device includes: a semiconductor substrate including an upper surface and a lower surface opposing each other and a drift layer of a first conductivity type; a base layer of a second conductivity type; an emitter layer of the first conductivity type and a contact layer of the second conductivity type; an active trench; dummy trenches; a trench gate electrode formed in the active trench; a dummy trench gate electrode formed in each of the dummy trenches; an embedded insulating film formed on the trench gate electrode in the active trench, formed on the dummy trench gate electrode in the dummy trench, and having an upper end lower than the upper surface; and an emitter electrode contacting the emitter layer on the upper surface and an inner wall of the active trench, and contacting the contact layer on the upper surface and an inner wall of the dummy trench.

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl

Abstract: A semiconductor device includes: a carrier stored layer; an upper-stage active portion disposed on a first insulating film along an inner wall of an upper portion of a trench penetrating the carrier stored layer, the upper-stage active portion being upper-stage polysilicon connected to a gate electrode; and lower-stage polysilicon disposed on a second insulating film along an inner wall of a lower portion of the trench, the lower-stage polysilicon provided with a third insulating film disposed between the upper-stage active portion and the lower-stage polysilicon. The lower end of the upper-stage active portion is positioned below the lower end of the carrier stored layer.

Abstract: A semiconductor device includes; a semiconductor substrate; an emitter electrode provided on the semiconductor substrate; a gate electrode provided on the semiconductor substrate; a drift layer of a first conduction type provided in the semiconductor substrate; a source layer of the first conduction type provided on an upper surface side of the semiconductor substrate; a base layer of a second conduction type provided on the upper surface side of the semiconductor substrate; a collector electrode provided below the semiconductor substrate; and a two-part dummy active trench including, at an upper part, an upper dummy part not connected with the gate electrode and including, at a lower part, a lower active part connected with the gate electrode and covered by an insulating film, in a trench of the semiconductor substrate, wherein a longitudinal length of the lower active part is larger than a width of the lower active part.

Abstract: A first principal electrode and a first control electrode pad are formed on a first principal surface of the semiconductor chip. A second principal electrode and a second control electrode pad are formed on a second principal surface of the semiconductor chip. The second principal electrode and the second control electrode pad are respectively bonded to first and second metal patterns of an insulating substrate. Bonding sections of first and second wires overlap a bonding section of the second principal electrode or the second control electrode pad in plan view. Thickness of the first and second metal patterns is 0.2 mm or less.

Abstract: A semiconductor device includes a semiconductor substrate having a drift layer of a first conductivity type and a collector layer of a second conductivity type. A first buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the drift layer and the collector layer and a second buffer layer having a higher impurity concentration peak than that of the drift layer is formed between the first buffer layer and the collector layer. A kurtosis of a peak of an impurity concentration of the second buffer layer is lower than a kurtosis of a peak of an impurity concentration of the first buffer layer.

Abstract: According to the disclosure, a semiconductor device includes a semiconductor substrate including an IGBT region and a diode region, a first electrode provided on an upper surface of the semiconductor substrate and a second electrode provided on a back surface of the semiconductor substrate, wherein the diode region includes an n-type drift layer, a p-type anode layer provided on an upper surface side of the drift layer, and an n-type cathode layer provided on a back surface side of the drift layer, a lifetime control region having crystal defect density higher than crystal defect density of other portions of the drift layer and including protons is provided on a back surface side relative to a center in a thickness direction of the semiconductor substrate among the drift layer, and a maximum value of donor concentration of the lifetime control region is equal to or less than 1.0×1015/cm3.

Abstract: A semiconductor device includes a first electrode and a second electrode. The first electrode is connected to a collector layer and a first portion on the collector layer side of a cathode layer. The second electrode is connected to a second portion of the cathode layer excluding the first portion. A work function of the first electrode is larger than a work function of the second electrode, and one of the first electrode and the second electrode and the semiconductor substrate sandwich another of the first electrode and the second electrode in a thickness direction of the semiconductor substrate.

Abstract: A diode region includes: an n-type first semiconductor layer provided on a second-main-surface side in the semiconductor substrate; an n-type second semiconductor layer provided on the first semiconductor layer; a p-type third semiconductor layer provided closer to a first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode that applies a first potential to the diode; a second main electrode that applies a second potential to the diode; and a dummy active trench gate provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer. The dummy active trench gate includes the third semiconductor layer that is not applied with the first potential to be in a floating state on at least one of two side surfaces, and the dummy active trench gate is applied with a gate potential of the transistor.

Abstract: When a positive gate voltage is applied to a first one of a first gate electrode and a second gate electrode, and current flows from a collector electrode to an emitter electrode, a semiconductor device applies a positive gate voltage to a second one of the first gate electrode and the second gate electrode. When a positive gate voltage is applied to the first one and current flows from the emitter electrode to the collector electrode, the semiconductor device applies voltage equal to or less than reference voltage to the second one.

Abstract: A semiconductor device includes: a semiconductor substrate including a front surface, a back surface that is opposite to the front surface, and a drift layer of a first conductive type disposed between the front surface and the back surface; a first diffusion layer of a second conductive type provided between the drift layer and the front surface; a second diffusion layer provided between the drift layer and the back surface; a first buffer layer of the first conductive type provided between the drift layer and the second diffusion layer, having a concentration higher than that of the drift layer, and into which a proton is injected; and a second buffer layer of the first conductive type provided between the first buffer layer and the second diffusion layer and having a concentration higher than that of the drift layer, wherein a peak concentration of the second buffer layer is higher than a peak concentration of the first buffer layer, an impurity concentration of the first buffer layer gradually decreases t

Abstract: All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

Abstract: Provided is a semiconductor device in which the reliability of the gate insulating film in a trench gate is improved. The semiconductor device includes a semiconductor substrate, a plurality of trench gates, and a gate electrode. The semiconductor substrate includes an active region and a wiring region. The trench gates extend from the first active region to the wiring region. The trench gates form parts of transistors in the active region. The gate electrode is provided in the wiring region and is electrically connected to the trench gates. The end portions of the trench gates are located in the wiring region. The gate electrode is provided so as to cover gate contact portions formed at the end portions of the trench gates. The gate electrode is electrically connected to trench gates via the gate contact portions. The plurality of trench gates extend only in one direction.

Abstract: A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12?3.5 is satisfied.