Abstract: A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12?3.5 is satisfied.

Abstract: There is provided a technique capable of reducing turn-on power losses. A semiconductor device includes: a semiconductor substrate including a drift layer; and a base layer, a contact layer, and a source layer which are provided in the semiconductor substrate. A gate portion is provided in a first trench, with a first gate insulation film therebetween. The first trench is in contact with the contact layer, the source layer, the base layer, and the drift layer. The gate portion is provided with a recessed portion with a bottom farther away from the base layer than a side thereof. A first insulation portion is provided in the recessed portion of the gate portion in the first trench.

Abstract: An object of the present disclosure is to reduce masks and to reduce the variation in the profile of an impurity layer in a semiconductor device. A method of manufacturing a semiconductor device includes a step (b) of forming a base layer on a first main surface side of a drift layer in an active region by implanting p-type impurity ions of using the first mask, a step of (c) of forming an emitter layer on the first main surface side of the base layer by implanting n-type impurity ions using the first mask, a step (d) of forming trenches after the steps (b) and (c), a step (e) of embedding a gate electrode inside the trenches, and a step (g) of converting a part of the emitter layer into a first contact layer by implanting the p-type impurity ions having a high dosage using a second mask.

Abstract: The present invention aims to provide a novel glycosyl hesperetin, which is significantly reduced in miscellaneous tastes characteristic of conventional products containing glycosyl hesperetin, and a method for producing the same and uses thereof; and the objects are solved by providing a glycosyl hesperetin which comprises glycosyl hesperetin in an amount of 90% or more by mass but less than 100% by mass, on a dry solid basis, but it does not substantially contain furfural, and a method for producing the same and uses thereof.

Abstract: Hysteresis of gate leakage is reduced in a semiconductor device with a structure including embedded electrodes below gate trench electrodes. A semiconductor device includes an active trench gate formed in a trench coming in contact with an emitter layer, a base layer, and a carrier storage layer to reach a drift layer. The active trench gate includes: a gate trench insulating film formed on an inner wall of the trench; and a gate trench electrode, and an embedded electrode below the gate trench electrode, the gate trench electrode and the embedded electrode being formed on the gate trench insulating film in the trench and being insulated from each other. The embedded electrode is lower in phosphorus concentration than the gate trench electrode.

Abstract: A semiconductor device includes: a semiconductor substrate including an upper surface and a lower surface opposing each other and a drift layer of a first conductivity type; a base layer of a second conductivity type; an emitter layer of the first conductivity type and a contact layer of the second conductivity type; an active trench; dummy trenches; a trench gate electrode formed in the active trench; a dummy trench gate electrode formed in each of the dummy trenches; an embedded insulating film formed on the trench gate electrode in the active trench, formed on the dummy trench gate electrode in the dummy trench, and having an upper end lower than the upper surface; and an emitter electrode contacting the emitter layer on the upper surface and an inner wall of the active trench, and contacting the contact layer on the upper surface and an inner wall of the dummy trench.

Abstract: An object is to provide a technique of improving productivity of a semiconductor device. A first buffer layer includes a first portion located in a thickness direction of a semiconductor substrate from a main surface and having a first peak of an N type impurity concentration and a second portion located farther away from the main surface than the first portion and having a second peak of an N type impurity concentration. A distance from the main surface to the first portion is equal to or smaller than 4.0 ?m, and a distance from the first portion to the second portion is equal to or larger than 14.5 ?m. An N type impurity concentration of a portion between the first portion and the second portion is higher than an N type impurity concentration of a drift layer.

Abstract: An object of the present disclosure is to provide a semiconductor device capable of lowering the threshold voltage without deteriorating the RBSOA tolerance and manufacturing variation. According to the present disclosure, the semiconductor device includes a drift layer of a first conductivity type, a carrier store layer of the first conductivity type, a base layer of a second conductivity type, an emitter layer of the first conductivity type provided on the first main surface side of the base layer, an active trench provided so as to extend through the emitter layer, the base layer, and the carrier store layer and reach the drift layer, a gate insulating film, a gate electrode, and a collector layer of the second conductivity type provided on a second main surface side of the drift layer, in which peak concentration of impurities in the base layer is 1.0E17 cm?3 or higher.

Abstract: A semiconductor device includes: a semiconductor substrate including a front surface, a back surface that is opposite to the front surface, and a drift layer of a first conductive type disposed between the front surface and the back surface; a first diffusion layer of a second conductive type provided between the drift layer and the front surface; a second diffusion layer provided between the drift layer and the back surface; a first buffer layer of the first conductive type provided between the drift layer and the second diffusion layer, having a concentration higher than that of the drift layer, and into which a proton is injected; and a second buffer layer of the first conductive type provided between the first buffer layer and the second diffusion layer and having a concentration higher than that of the drift layer, wherein a peak concentration of the second buffer layer is higher than a peak concentration of the first buffer layer, an impurity concentration of the first buffer layer gradually decreases t

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate including at least a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type provided in the upper layer of the third semiconductor layer; a first gate trench extending in the thickness direction through the fourth, third, and second semiconductor layers to the inside of the first semiconductor layer; an interlayer insulating film; a first main electrode provided in contact with the fourth semiconductor layer; and a second main electrode provided on the side opposite the first main electrode. The first gate trench includes a first gate electrode on the lower side and a second gate electrode on the upper side.

Abstract: A semiconductor device includes an insulated gate bipolar transistor region having a base layer of a second conductivity type provided in a surface layer of the semiconductor substrate on a first main surface side, an emitter layer of a first conductivity type having an impurity concentration higher than that of a drift layer selectively provided in the surface layer of the base layer on the first main surface side, a plurality of gate electrodes facing the emitter layer, the base layer, and the drift layer via gate insulating films, a counter-doped layer, having an impurity concentration of the second conductivity type higher than that of the base layer and an impurity concentration of the first conductivity type higher than that of the drift layer, and a collector layer of the second conductivity type provided in the surface layer of the semiconductor substrate on a second main surface side.

Abstract: A semiconductor device includes; a semiconductor substrate; an emitter electrode provided on the semiconductor substrate; a gate electrode provided on the semiconductor substrate; a drift layer of a first conduction type provided in the semiconductor substrate; a source layer of the first conduction type provided on an upper surface side of the semiconductor substrate; a base layer of a second conduction type provided on the upper surface side of the semiconductor substrate; a collector electrode provided below the semiconductor substrate; and a two-part dummy active trench including, at an upper part, an upper dummy part not connected with the gate electrode and including, at a lower part, a lower active part connected with the gate electrode and covered by an insulating film, in a trench of the semiconductor substrate, wherein a longitudinal length of the lower active part is larger than a width of the lower active part.

Abstract: A semiconductor device includes: a carrier stored layer; an upper-stage active portion disposed on a first insulating film along an inner wall of an upper portion of a trench penetrating the carrier stored layer, the upper-stage active portion being upper-stage polysilicon connected to a gate electrode; and lower-stage polysilicon disposed on a second insulating film along an inner wall of a lower portion of the trench, the lower-stage polysilicon provided with a third insulating film disposed between the upper-stage active portion and the lower-stage polysilicon. The lower end of the upper-stage active portion is positioned below the lower end of the carrier stored layer.

Abstract: The semiconductor substrate has a first principal surface and a second principal surface. The base contact layer is arranged between the base layer and the first principal surface, and forms a part of the first principal surface. The anode contact region is arranged between the anode layer and the first principal surface, forms a part of the first principal surface, and has a second conductivity type impurity concentration peak value higher than that of the anode layer. The anode contact region includes a first anode contact layer having a lower net concentration and a higher first conductivity type impurity concentration than the base contact layer.

Abstract: In a mesa region sandwiched between adjacent active trenches among mesa regions that are regions each sandwiched between adjacent trenches, a third semiconductor layer has regions discretely arranged in a first direction so as to be in contact with one active trench of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction so as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched between the adjacent active trenches, a fourth semiconductor layer is disposed between the third semiconductor layer on the side in contact with the one active trench and the third semiconductor layer on the side in contact with the other active trench in plan view and between the respective regions of the third semiconductor layer discrete in the first direction.

Abstract: A semiconductor device includes: a drift layer of a first conduction type provided in a semiconductor substrate having a first principal plane and a second principal plane opposed to the first principal plane; a first semiconductor layer of a second conduction type provided between the first principal plane of the semiconductor substrate and the drift layer and having impurity concentration higher than impurity concentration of the drift layer; a first buffer layer of a first conduction type provided between the second principal plane of the semiconductor substrate and the drift layer and having hydrogen-induced donors with impurity concentration higher than impurity concentration of the drift layer; and a second semiconductor layer of a first conduction type or a second conduction type provided between the second principal plane of the semiconductor substrate and the first buffer layer and having impurity concentration higher than impurity concentration of the drift layer, wherein the first buffer layer incl

Abstract: A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12?3.5 is satisfied.

Abstract: Provided is a semiconductor device in which the reliability of the gate insulating film in a trench gate is improved. The semiconductor device includes a semiconductor substrate, a plurality of trench gates, and a gate electrode. The semiconductor substrate includes an active region and a wiring region. The trench gates extend from the first active region to the wiring region. The trench gates form parts of transistors in the active region. The gate electrode is provided in the wiring region and is electrically connected to the trench gates. The end portions of the trench gates are located in the wiring region. The gate electrode is provided so as to cover gate contact portions formed at the end portions of the trench gates. The gate electrode is electrically connected to trench gates via the gate contact portions. The plurality of trench gates extend only in one direction.

Abstract: An object of the present disclosure is to provide a semiconductor device capable of lowering the threshold voltage without deteriorating the RBSOA tolerance and manufacturing variation. According to the present disclosure, the semiconductor device includes a drift layer of a first conductivity type, a carrier store layer of the first conductivity type, a base layer of a second conductivity type, an emitter layer of the first conductivity type provided on the first main surface side of the base layer, an active trench provided so as to extend through the emitter layer, the base layer, and the carrier store layer and reach the drift layer, a gate insulating film, a gate electrode, and a collector layer of the second conductivity type provided on a second main surface side of the drift layer, in which peak concentration of impurities in the base layer is 1.0E17 cm?3 or higher.

Abstract: An object is to provide a technique of improving productivity of a semiconductor device. A first buffer layer includes a first portion located in a thickness direction of a semiconductor substrate from a main surface and having a first peak of an N type impurity concentration and a second portion located farther away from the main surface than the first portion and having a second peak of an N type impurity concentration. A distance from the main surface to the first portion is equal to or smaller than 4.0 ?m, and a distance from the first portion to the second portion is equal to or larger than 14.5 ?m. An N type impurity concentration of a portion between the first portion and the second portion is higher than an N type impurity concentration of a drift layer.