Patents by Inventor Koichiro Hayashi

Koichiro Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230347544
    Abstract: Provided is a workpiece cutting device capable of reliably cutting a workpiece in a short period of time without damaging portions other than seams and without leading to an increase in size of the device in a case where the device is used to cut a workpiece formed into a sheet shape by partially coupling a plurality of small pieces to each other, for example. A workpiece cutting device that cuts a sheet-shaped or thin plate-shaped workpiece into a first-side workpiece and a second-side workpiece includes a securing mechanism that secures the first-side workpiece, a gripping and turning mechanism that grips the second-side workpiece and turns the second-side workpiece about a seam with the first-side workpiece as an axis, and a separating piece insertion mechanism that separates the first-side workpiece and the second-side workpiece at a vulnerable portion formed at the seam through a turning operation of the second-side workpiece performed by the gripping and turning mechanism.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 2, 2023
    Applicant: IHI CORPORATION
    Inventors: Takuya SUNAKAWA, Koichiro HAYASHI, Kensuke HIRATA, Wataru UEDA
  • Publication number: 20230093764
    Abstract: A medical honeycomb structure lacking at least a portion of an outer peripheral side wall of a honeycomb structure that includes a plurality of through-holes extending in one direction, wherein sites lacking the outer peripheral side wall have a plurality of grooves, and have a plurality of planes including distant surfaces of groove side walls flanked by the grooves.
    Type: Application
    Filed: March 5, 2021
    Publication date: March 23, 2023
    Applicants: Kunio ISHIKAWA, GC Corporation
    Inventors: Kunio ISHIKAWA, Koichiro HAYASHI, Akira TSUCHIYA, Ryo KISHIDA, Yasuharu NAKASHIMA
  • Publication number: 20220065400
    Abstract: A tank production method for preventing generation of non-uniform stacked portions in a sheet layer while securing the strength of the tank, the method including a winding step of winding resin-impregnated fiber sheets to form a sheet layer with a predetermined thickness. The winding step includes divided winding steps of winding divided fiber sheets obtained by dividing a fiber sheet into a plurality of divided fiber sheets having a length shorter than the length required to form the sheet layer with the predetermined thickness.
    Type: Application
    Filed: November 9, 2021
    Publication date: March 3, 2022
    Inventors: Tatsunori SHINDO, Koichiro HAYASHI, Takashi INOH
  • Patent number: 11204132
    Abstract: A tank production method for preventing generation of non-uniform stacked portions in a sheet layer while securing the strength of the tank, the method including a winding step of winding resin-impregnated fiber sheets to form a sheet layer with a predetermined thickness. The winding step includes divided winding steps of winding divided fiber sheets obtained by dividing a fiber sheet into a plurality of divided fiber sheets having a length shorter than the length required to form the sheet layer with the predetermined thickness.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 21, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tatsunori Shindo, Koichiro Hayashi, Takashi Inoh
  • Patent number: 11177277
    Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: November 16, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
  • Patent number: 11081167
    Abstract: Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 3, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi
  • Patent number: 11081192
    Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 3, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Publication number: 20210142858
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Publication number: 20210134828
    Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
  • Publication number: 20210134375
    Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10984874
    Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
  • Patent number: 10885984
    Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Publication number: 20200124521
    Abstract: The present invention relates to a fluorescent probe for flow cytometry that includes a carrier molecule and porphyrin bound to the carrier molecule and in which an excitation wavelength of the fluorescent probe for flow cytometry is in a range of 350 to 650 nm. The present invention also relates to a method for screening fluorescence-labeled cells using a flow cytometer that includes a step of fluorescently labeling cells with a fluorescent probe for flow cytometry and a step of screening fluorescence-labeled cells labeled with the fluorescent probe for flow cytometry using a flow cytometer, and in which the screening of the fluorescence-labeled cells using a flow cytometer is performed by irradiating the fluorescence-labeled cells with excitation light with a wavelength of 350 to 650 nm and detecting fluorescence.
    Type: Application
    Filed: February 10, 2017
    Publication date: April 23, 2020
    Inventors: Koichiro HAYASHI, Wataru SAKAMOTO, Toshinobu YOGO, Hiroki MARUOKA
  • Publication number: 20190137396
    Abstract: The present invention relates to a fluorescent probe including a carrier molecule, a fluorescent dye a bound to the carrier molecule, and a fluorescent dye b bound to the carrier molecule in which the excitation wavelengths of the fluorescent dyes a and b are different, and FRET does not occur between the fluorescent dyes a and b. The present invention also relates to a method for detecting fluorescence that includes a step of labeling target cells with the fluorescent probe, and a step of irradiating the target cells labeled with the fluorescent probe with excitation light and observing the fluorescence from the fluorescent probe.
    Type: Application
    Filed: February 10, 2017
    Publication date: May 9, 2019
    Applicants: National University Corporation Nagoya University, KURASHIKI BOSEKI KABUSHIKI KAISHA
    Inventors: Koichiro HAYASHI, Wataru SAKAMOTO, Toshinobu YOGO, Hiroki MARUOKA
  • Publication number: 20190128477
    Abstract: A tank production method for preventing generation of non-uniform stacked portions in a sheet layer while securing the strength of the tank, the method including a winding step of winding resin-impregnated fiber sheets to form a sheet layer with a predetermined thickness. The winding step includes divided winding steps of winding divided fiber sheets obtained by dividing a fiber sheet into a plurality of divided fiber sheets having a length shorter than the length required to form the sheet layer with the predetermined thickness.
    Type: Application
    Filed: September 12, 2018
    Publication date: May 2, 2019
    Inventors: Tatsunori SHINDO, Koichiro HAYASHI, Takashi INOH
  • Patent number: 10126765
    Abstract: A semiconductor device including a first internal voltage generating circuit that includes a capacitor including a first electrode and a second electrode, and the first internal voltage generating circuit to generate an internal voltage by charging the capacitor to a first voltage and applying a second voltage to the first electrode of the capacitor to generate a third voltage that is greater than the first and the second voltages on the second electrode in absolute value, and a control circuit to perform a control by applying a fourth voltage that is less than the first voltage to the capacitor when the first internal voltage generating circuit is in a standby state.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: November 13, 2018
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Koichiro Hayashi
  • Publication number: 20180180222
    Abstract: A high pressure tank includes a liner, a reinforcing layer which includes a first thermosetting resin and fibers and is formed on the liner, and a protective layer which includes a second thermosetting resin having a lower gelling temperature than the a gelling temperature of first thermosetting resin and is formed on the reinforcing layer.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 28, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki UEDA, Masayoshi TAKAMI, Koichiro HAYASHI, Takashi INOH
  • Patent number: 9890483
    Abstract: A fiber-reinforced composite material for increasing adhesive strength between a first composite material layer including a fibrous substrate with reinforcement fiber bundles arranged crosswise, and a second composite material layer including second reinforcement fibers arranged randomly. The first composite material layer including a fibrous substrate having reinforcement fiber bundles crossing and being drawn and aligned first reinforcement fibers; and first thermoplastic resin, with at least each of the reinforcement fiber bundles is impregnated; and a second composite material layer including second reinforcement fibers arranged randomly in second thermoplastic resin. The first composite material layer and the second composite material layer bonded to each other. The first composite material layer has bores on at least a surface thereof that is to be bonded with the second composite material layer. The second reinforcement fibers and the second thermoplastic resin enter into the bores.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: February 13, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Koichiro Hayashi
  • Patent number: 9815194
    Abstract: An end effector includes a pair of machining tools. The pair of machining tools is separated by an interval in one direction perpendicular to a tool rotational axis and rotatable around the tool rotational axis. The pair of machining tools is position-controlled, and is force-controlled in a machining direction perpendicular to the one direction and an axial direction of the tool rotational axis, and is torque-controlled around the tool rotational axis.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: November 14, 2017
    Assignee: IHI CORPORATION
    Inventors: Mitsuharu Sonehara, Koichiro Hayashi
  • Patent number: 9620177
    Abstract: An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from each other, an internal voltage generating circuit that generates the power supply voltage with reference to a reference potential generated by the reference potential generating circuit, and a control circuit that selects a reference potential to be generated by the reference potential generating circuit.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: April 11, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventor: Koichiro Hayashi