Patents by Inventor Koichiro Hayashi
Koichiro Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230347544Abstract: Provided is a workpiece cutting device capable of reliably cutting a workpiece in a short period of time without damaging portions other than seams and without leading to an increase in size of the device in a case where the device is used to cut a workpiece formed into a sheet shape by partially coupling a plurality of small pieces to each other, for example. A workpiece cutting device that cuts a sheet-shaped or thin plate-shaped workpiece into a first-side workpiece and a second-side workpiece includes a securing mechanism that secures the first-side workpiece, a gripping and turning mechanism that grips the second-side workpiece and turns the second-side workpiece about a seam with the first-side workpiece as an axis, and a separating piece insertion mechanism that separates the first-side workpiece and the second-side workpiece at a vulnerable portion formed at the seam through a turning operation of the second-side workpiece performed by the gripping and turning mechanism.Type: ApplicationFiled: July 7, 2023Publication date: November 2, 2023Applicant: IHI CORPORATIONInventors: Takuya SUNAKAWA, Koichiro HAYASHI, Kensuke HIRATA, Wataru UEDA
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Publication number: 20230093764Abstract: A medical honeycomb structure lacking at least a portion of an outer peripheral side wall of a honeycomb structure that includes a plurality of through-holes extending in one direction, wherein sites lacking the outer peripheral side wall have a plurality of grooves, and have a plurality of planes including distant surfaces of groove side walls flanked by the grooves.Type: ApplicationFiled: March 5, 2021Publication date: March 23, 2023Applicants: Kunio ISHIKAWA, GC CorporationInventors: Kunio ISHIKAWA, Koichiro HAYASHI, Akira TSUCHIYA, Ryo KISHIDA, Yasuharu NAKASHIMA
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Publication number: 20220065400Abstract: A tank production method for preventing generation of non-uniform stacked portions in a sheet layer while securing the strength of the tank, the method including a winding step of winding resin-impregnated fiber sheets to form a sheet layer with a predetermined thickness. The winding step includes divided winding steps of winding divided fiber sheets obtained by dividing a fiber sheet into a plurality of divided fiber sheets having a length shorter than the length required to form the sheet layer with the predetermined thickness.Type: ApplicationFiled: November 9, 2021Publication date: March 3, 2022Inventors: Tatsunori SHINDO, Koichiro HAYASHI, Takashi INOH
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Patent number: 11204132Abstract: A tank production method for preventing generation of non-uniform stacked portions in a sheet layer while securing the strength of the tank, the method including a winding step of winding resin-impregnated fiber sheets to form a sheet layer with a predetermined thickness. The winding step includes divided winding steps of winding divided fiber sheets obtained by dividing a fiber sheet into a plurality of divided fiber sheets having a length shorter than the length required to form the sheet layer with the predetermined thickness.Type: GrantFiled: September 12, 2018Date of Patent: December 21, 2021Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tatsunori Shindo, Koichiro Hayashi, Takashi Inoh
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Patent number: 11177277Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.Type: GrantFiled: November 6, 2019Date of Patent: November 16, 2021Assignee: SanDisk Technologies LLCInventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
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Patent number: 11081167Abstract: Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.Type: GrantFiled: June 26, 2020Date of Patent: August 3, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Hiroki Yabe, Koichiro Hayashi
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Patent number: 11081192Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.Type: GrantFiled: October 30, 2019Date of Patent: August 3, 2021Assignee: SanDiskTechnologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
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Publication number: 20210142858Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Applicant: SanDisk Technologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
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Publication number: 20210134828Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.Type: ApplicationFiled: November 6, 2019Publication date: May 6, 2021Applicant: SanDisk Technologies LLCInventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
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Publication number: 20210134375Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.Type: ApplicationFiled: October 30, 2019Publication date: May 6, 2021Applicant: SanDisk Technologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
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Patent number: 10984874Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.Type: GrantFiled: November 13, 2019Date of Patent: April 20, 2021Assignee: SanDisk Technologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
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Patent number: 10885984Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.Type: GrantFiled: October 30, 2019Date of Patent: January 5, 2021Assignee: SanDisk Technologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
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Publication number: 20200124521Abstract: The present invention relates to a fluorescent probe for flow cytometry that includes a carrier molecule and porphyrin bound to the carrier molecule and in which an excitation wavelength of the fluorescent probe for flow cytometry is in a range of 350 to 650 nm. The present invention also relates to a method for screening fluorescence-labeled cells using a flow cytometer that includes a step of fluorescently labeling cells with a fluorescent probe for flow cytometry and a step of screening fluorescence-labeled cells labeled with the fluorescent probe for flow cytometry using a flow cytometer, and in which the screening of the fluorescence-labeled cells using a flow cytometer is performed by irradiating the fluorescence-labeled cells with excitation light with a wavelength of 350 to 650 nm and detecting fluorescence.Type: ApplicationFiled: February 10, 2017Publication date: April 23, 2020Inventors: Koichiro HAYASHI, Wataru SAKAMOTO, Toshinobu YOGO, Hiroki MARUOKA
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Publication number: 20190137396Abstract: The present invention relates to a fluorescent probe including a carrier molecule, a fluorescent dye a bound to the carrier molecule, and a fluorescent dye b bound to the carrier molecule in which the excitation wavelengths of the fluorescent dyes a and b are different, and FRET does not occur between the fluorescent dyes a and b. The present invention also relates to a method for detecting fluorescence that includes a step of labeling target cells with the fluorescent probe, and a step of irradiating the target cells labeled with the fluorescent probe with excitation light and observing the fluorescence from the fluorescent probe.Type: ApplicationFiled: February 10, 2017Publication date: May 9, 2019Applicants: National University Corporation Nagoya University, KURASHIKI BOSEKI KABUSHIKI KAISHAInventors: Koichiro HAYASHI, Wataru SAKAMOTO, Toshinobu YOGO, Hiroki MARUOKA
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Publication number: 20190128477Abstract: A tank production method for preventing generation of non-uniform stacked portions in a sheet layer while securing the strength of the tank, the method including a winding step of winding resin-impregnated fiber sheets to form a sheet layer with a predetermined thickness. The winding step includes divided winding steps of winding divided fiber sheets obtained by dividing a fiber sheet into a plurality of divided fiber sheets having a length shorter than the length required to form the sheet layer with the predetermined thickness.Type: ApplicationFiled: September 12, 2018Publication date: May 2, 2019Inventors: Tatsunori SHINDO, Koichiro HAYASHI, Takashi INOH
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Patent number: 10126765Abstract: A semiconductor device including a first internal voltage generating circuit that includes a capacitor including a first electrode and a second electrode, and the first internal voltage generating circuit to generate an internal voltage by charging the capacitor to a first voltage and applying a second voltage to the first electrode of the capacitor to generate a third voltage that is greater than the first and the second voltages on the second electrode in absolute value, and a control circuit to perform a control by applying a fourth voltage that is less than the first voltage to the capacitor when the first internal voltage generating circuit is in a standby state.Type: GrantFiled: August 8, 2016Date of Patent: November 13, 2018Assignee: LONGITUDE LICENSING LIMITEDInventor: Koichiro Hayashi
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Publication number: 20180180222Abstract: A high pressure tank includes a liner, a reinforcing layer which includes a first thermosetting resin and fibers and is formed on the liner, and a protective layer which includes a second thermosetting resin having a lower gelling temperature than the a gelling temperature of first thermosetting resin and is formed on the reinforcing layer.Type: ApplicationFiled: December 15, 2017Publication date: June 28, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Naoki UEDA, Masayoshi TAKAMI, Koichiro HAYASHI, Takashi INOH
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Patent number: 9890483Abstract: A fiber-reinforced composite material for increasing adhesive strength between a first composite material layer including a fibrous substrate with reinforcement fiber bundles arranged crosswise, and a second composite material layer including second reinforcement fibers arranged randomly. The first composite material layer including a fibrous substrate having reinforcement fiber bundles crossing and being drawn and aligned first reinforcement fibers; and first thermoplastic resin, with at least each of the reinforcement fiber bundles is impregnated; and a second composite material layer including second reinforcement fibers arranged randomly in second thermoplastic resin. The first composite material layer and the second composite material layer bonded to each other. The first composite material layer has bores on at least a surface thereof that is to be bonded with the second composite material layer. The second reinforcement fibers and the second thermoplastic resin enter into the bores.Type: GrantFiled: February 5, 2015Date of Patent: February 13, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Koichiro Hayashi
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Patent number: 9815194Abstract: An end effector includes a pair of machining tools. The pair of machining tools is separated by an interval in one direction perpendicular to a tool rotational axis and rotatable around the tool rotational axis. The pair of machining tools is position-controlled, and is force-controlled in a machining direction perpendicular to the one direction and an axial direction of the tool rotational axis, and is torque-controlled around the tool rotational axis.Type: GrantFiled: August 20, 2015Date of Patent: November 14, 2017Assignee: IHI CORPORATIONInventors: Mitsuharu Sonehara, Koichiro Hayashi
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Patent number: 9620177Abstract: An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from each other, an internal voltage generating circuit that generates the power supply voltage with reference to a reference potential generated by the reference potential generating circuit, and a control circuit that selects a reference potential to be generated by the reference potential generating circuit.Type: GrantFiled: June 3, 2010Date of Patent: April 11, 2017Assignee: Longitude Semiconductor S.a.r.l.Inventor: Koichiro Hayashi