Patents by Inventor Koichiro Hayashi
Koichiro Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160342164Abstract: A semiconductor device including a first internal voltage generating circuit that includes a capacitor including a first electrode and a second electrode, and the first internal voltage generating circuit to generate an internal voltage by charging the capacitor to a first voltage and applying a second voltage to the first electrode of the capacitor to generate a third voltage that is greater than the first and the second voltages on the second electrode in absolute value, and a control circuit to perform a control by applying a fourth voltage that is less than the first voltage to the capacitor when the first internal voltage generating circuit is in a standby state.Type: ApplicationFiled: August 8, 2016Publication date: November 24, 2016Inventor: Koichiro Hayashi
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Patent number: 9411347Abstract: A semiconductor device including a first internal voltage generating circuit that includes a capacitor including a first electrode and a second electrode, and the first internal voltage generating circuit to generate an internal voltage by charging the capacitor to a first voltage and applying a second voltage to the first electrode of the capacitor to generate a third voltage that is greater than the first and the second voltages on the second electrode in absolute value, and a control circuit to perform a control by applying a fourth voltage that is less than the first voltage to the capacitor when the first internal voltage generating circuit is in a standby state.Type: GrantFiled: March 20, 2015Date of Patent: August 9, 2016Assignee: PS4 LUXCO S.A.R.L.Inventor: Koichiro Hayashi
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Publication number: 20150352716Abstract: An end effector includes a pair of machining tools. The pair of machining tools is separated by an interval in one direction perpendicular to a tool rotational axis and rotatable around the tool rotational axis. The pair of machining tools is position-controlled, and is force-controlled in a machining direction perpendicular to the one direction and an axial direction of the tool rotational axis, and is torque-controlled around the tool rotational axis.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Applicant: IHI CORPORATIONInventors: Mitsuharu SONEHARA, Koichiro HAYASHI
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Patent number: 9207701Abstract: A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.Type: GrantFiled: September 9, 2014Date of Patent: December 8, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Koichiro Hayashi, Hitoshi Tanaka
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Publication number: 20150286229Abstract: A semiconductor device including a first internal voltage generating circuit that includes a capacitor including a first electrode and a second electrode, and the first internal voltage generating circuit to generate an internal voltage by charging the capacitor to a first voltage and applying a second voltage to the first electrode of the capacitor to generate a third voltage that is greater than the first and the second voltages on the second electrode in absolute value, and a control circuit to perform a control by applying a fourth voltage that is less than the first voltage to the capacitor when the first internal voltage generating circuit is in a standby state.Type: ApplicationFiled: March 20, 2015Publication date: October 8, 2015Inventor: Koichiro Hayashi
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Publication number: 20150240396Abstract: Provided is a fiber-reinforced composite material capable of increasing the adhesive strength between a first composite material layer including a fibrous substrate in which reinforcement fiber bundles are arranged crosswise, and a second composite material layer including second reinforcement fibers that are arranged at random, and a method for manufacturing the same. A fiber-reinforced composite material includes: a first composite material layer 11A including: a fibrous substrate 14 including reinforcement fiber bundles 13 crossing, the reinforcement fiber bundles being drawn and aligned first reinforcement fibers 12; and first thermoplastic resin, with which at least each of the reinforcement fiber bundles 13 is impregnated; and a second composite material layer 41A including second reinforcement fibers 42 that are arranged at random in second thermoplastic resin 46.Type: ApplicationFiled: February 5, 2015Publication date: August 27, 2015Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Koichiro HAYASHI
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Patent number: 8987937Abstract: To include an internal voltage generating circuit that includes a capacitor having a first electrode and a second electrode and generates an internal voltage by repeating a charge operation for charging the capacitor to a VDD level and a discharge operation for applying the VDD level to the first electrode of the capacitor to generate a voltage of two times the VDD level on the second electrode, and a control circuit that performs a control to apply a voltage that is lower than the VDD level to the capacitor when the internal voltage generating circuit is in a standby state. According to the present invention, when the internal voltage generating circuit is in a standby state, because a voltage applied to both ends of the capacitor is reduced, it is possible to reduce the power consumption due to a leakage current.Type: GrantFiled: November 29, 2010Date of Patent: March 24, 2015Assignee: PS4 Luxco S.a.r.l.Inventor: Koichiro Hayashi
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Publication number: 20140375369Abstract: A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.Type: ApplicationFiled: September 9, 2014Publication date: December 25, 2014Applicant: PS4 LUXCO S.A.R.L.Inventors: Koichiro HAYASHI, Hitoshi TANAKA
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Patent number: 8860499Abstract: A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.Type: GrantFiled: June 7, 2013Date of Patent: October 14, 2014Assignee: PS4 Luxco S.a.r.l.Inventors: Koichiro Hayashi, Hitoshi Tanaka
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Publication number: 20130265103Abstract: A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.Type: ApplicationFiled: June 7, 2013Publication date: October 10, 2013Inventors: Koichiro HAYASHI, Hitoshi TANAKA
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Patent number: 8553487Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.Type: GrantFiled: December 27, 2012Date of Patent: October 8, 2013Assignee: Elpida Memory, Inc.Inventor: Koichiro Hayashi
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Patent number: 8493132Abstract: A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.Type: GrantFiled: March 20, 2008Date of Patent: July 23, 2013Assignee: Elpida Memory, Inc.Inventors: Koichiro Hayashi, Hitoshi Tanaka
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Patent number: 8358556Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.Type: GrantFiled: May 25, 2010Date of Patent: January 22, 2013Assignee: Elpida Memory, Inc.Inventor: Koichiro Hayashi
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Patent number: 8036060Abstract: In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and N?2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an internal memory array successively. The SDRAM includes a DLL circuit for aligning phase of an internal clock signal with that of an external clock signal that is externally supplied, and a DLL control circuit for exercising control so as to halt operation of the DLL circuit in an interval in which the address signal becomes active one or more times and N?1 times or fewer, this interval being included in an interval in which the signal RAS becomes active N times. The DLL control circuit counts the signal RAS and decodes the value of the count. Operation of the DLL circuit is halted while a prescribed range of count values is being decoded.Type: GrantFiled: April 21, 2009Date of Patent: October 11, 2011Assignee: Elpida Memory, Inc.Inventor: Koichiro Hayashi
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Publication number: 20110127850Abstract: To include an internal voltage generating circuit that includes a capacitor having a first electrode and a second electrode and generates an internal voltage by repeating a charge operation for charging the capacitor to a VDD level and a discharge operation for applying the VDD level to the first electrode of the capacitor to generate a voltage of two times the VDD level on the second electrode, and a control circuit that performs a control to apply a voltage that is lower than the VDD level to the capacitor when the internal voltage generating circuit is in a standby state. According to the present invention, when the internal voltage generating circuit is in a standby state, because a voltage applied to both ends of the capacitor is reduced, it is possible to reduce the power consumption due to a leakage current.Type: ApplicationFiled: November 29, 2010Publication date: June 2, 2011Applicant: Elpida Memory, Inc.Inventor: Koichiro Hayashi
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Patent number: 7869299Abstract: An internal-voltage generating circuit includes a plurality of generating units connected in cascade, out of the plurality of generating units, a generating unit of relatively lower level is activated by an output of a generating unit of relatively higher level. According to the present invention, because the plural voltage generating units are connected in cascade, the voltage generating unit of lower level is not activated unless the voltage generating unit of higher level is activated. Therefore, at least the voltage generating unit of the second level and the subsequent voltage generating units consume very small power during the standby time. Consequently, total power consumption of the internal-voltage generating circuit can be reduced.Type: GrantFiled: October 28, 2008Date of Patent: January 11, 2011Assignee: Elpida Memory, Inc.Inventors: Koichiro Hayashi, Hitoshi Tanaka
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Publication number: 20100309735Abstract: An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from each other, an internal voltage generating circuit that generates the power supply voltage with reference to a reference potential generated by the reference potential generating circuit, and a control circuit that selects a reference potential to be generated by the reference potential generating circuit.Type: ApplicationFiled: June 3, 2010Publication date: December 9, 2010Applicant: Elpida Memory, Inc.Inventor: Koichiro Hayashi
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Publication number: 20100301949Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.Type: ApplicationFiled: May 25, 2010Publication date: December 2, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Koichiro HAYASHI
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Patent number: 7750659Abstract: A voltage detecting circuit detects a voltage between first and second wirings, and comprises at least first and second transistors connected in series between the first and second wirings, wherein a first reference voltage is supplied to a gate of the first transistor, a gate and a drain of the second transistor are short-circuited, and a detection signal is output from a connection point between a drain of the first transistor and a source of the second transistor.Type: GrantFiled: October 28, 2008Date of Patent: July 6, 2010Assignee: Elpida Memory, Inc.Inventors: Koichiro Hayashi, Hitoshi Tanaka
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Publication number: 20100142293Abstract: In a boosting voltage generating circuit, a boosting circuit unit generates boosting voltage according to a value of boosting voltage output by the boosting voltage generating circuit and an auxiliary boosting circuit unit supplies, immediately before electric current is consumed by a load supplied with the boosting voltage, voltage higher than the boosting voltage corresponding to the amount of current consumed by the load, to the load. The auxiliary boosting circuit unit raises the voltage supplied to the load to an optimum amount before the boosting voltage drops.Type: ApplicationFiled: December 3, 2009Publication date: June 10, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Koichiro Hayashi