Abstract: A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

Abstract: A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance element (1) whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element (2) that steers current flowing through the variable resistance element (1) when the electric pulses are applied, the current steering element (2) includes: a first electrode (32); a second electrode (31); and a current steering layer (33) interposed between the first electrode (32) and the second electrode (31). When the current steering layer (33) includes SiNx (0<x?0.

Abstract: A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

Abstract: A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.

Abstract: A method of manufacturing a memory cell array in which first conductive layers (2) and second conductive layers (14) extend above a semiconductor substrate (1) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element (10) and a variable resistance element (23) electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers (2) and the second conductive layers (14).

Abstract: A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises ?-tungsten.

Abstract: A nonvolatile memory element includes a first electrode (103) formed on a substrate (101), a resistance variable layer (108) and a second electrode (107), wherein the resistance variable layer has a multi-layer structure including at least three layers which are a first transition metal oxide layer (104), a second transition metal oxide layer (106) which is higher in oxygen concentration than the first transition metal oxide layer (104), and a transition metal oxynitride layer (105). The second transition metal oxide layer (106) is in contact with either one of the first electrode (103) and the second electrode (107). The transition metal oxynitride layer (105) is provided between the first transition metal oxide layer (104) and the second transition metal oxide layer (106).

Abstract: In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the first SiOCH layer is treated to change the surface section of the first SiOCH layer to a second SiOCH layer which features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer and an oxygen (O) density higher than that of the first SiOCH layer. Finally, a silicon dioxide (SiO2) layer is formed on the second SiOCH layer.

Abstract: An improved SIV resistance and an improved EM resistance are achieved in the coupling structure containing copper films. A semiconductor device includes: a semiconductor substrate; a second insulating layer formed on or over the semiconductor substrate; a second barrier metal film, formed on the second insulating film, and being capable of preventing copper from diffusing into the second insulating film; and an electrically conducting film formed on the second barrier metal film so as to be in contact with the second barrier metal film, and containing copper and carbon, wherein a distribution of carbon concentration along a depositing direction in the second electrically conducting film includes a first peak and a second peak.

Abstract: In a current rectifying element (10), a barrier height ?A of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height ?B of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1<X2). Therefore, the barrier layer (11) has a barrier height in which the shape changes in a stepwise manner and the height of the center region 14 is large.

Abstract: A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer, into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

Abstract: A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

Abstract: Memory elements (3) arranged in matrix in a memory apparatus (21), each includes a resistance variable element (1) which changes an electrical resistance value in response to an applied electrical pulse having a positive polarity or a negative polarity and maintains the changed electrical resistance value, and a current suppressing element (2) for suppressing a current flowing when the electrical pulse is applied to the resistance variable element. The current suppressing element includes a first electrode, a second electrode, and a current suppressing layer provided between the first electrode and the second electrode, and the current suppressing layer comprises SiNx (x: positive actual number).

Abstract: A multilevel interconnect structure in a semiconductor device comprises a first insulating layer (2) formed on a semiconductor wafer (1), a Cu interconnect layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu interconnect layer (4), and a metal oxide layer (5) formed at an interface between the Cu interconnect layer (4) and the second insulating layer (6). The metal oxide layer (5) is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer (4) and then heat-treating the plated layer in an oxidizing atmosphere.

Abstract: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.

Abstract: A method for manufacturing a semiconductor device is provided which includes performing an electroplating step to fill concavities formed on a substrate. The electroplating step further includes: performing a first electroplating step; performing a first reverse bias step; performing a second electroplating step; performing a second reverse bias step; and a third electroplating step. The polarity of the first and the second reverse bias steps is different from that of the first electroplating step. A difference between the third current density and the fourth current density is larger than a difference between the first current density and the second current density.

Abstract: The present invention provides a semiconductor device having interconnects, reduced in leakage current between the interconnects and improved in the TDDB characteristic, which comprises an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, comprising a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.

Abstract: A semiconductor device having interconnects is reduced in leakage current between the interconnects and improved in the TDDB characteristic. It includes an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, including a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.

Abstract: Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.

Abstract: An electrochemical processing apparatus is provided, in which a substrate and an anode placed in a chamber are partitioned into a cathode region including the substrate and an anode region including the anode by placing a multi-layered structure of a filtration film and a cation exchange film so that the filtration film is positioned on the substrate side. A plating solution containing additives is introduced into the cathode region, whereby a substrate is plated.