Patents by Inventor Koji Arita

Koji Arita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6333528
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: December 25, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6326315
    Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (“RRA”) technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: December 4, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Kiyoshi Uchiyama, Koji Arita, Narayan Solayappan, Carlos A. Paz de Araujo
  • Publication number: 20010041372
    Abstract: A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1−xZrx)O2, wherein 0≦x≦1.
    Type: Application
    Filed: March 29, 2001
    Publication date: November 15, 2001
    Applicant: Symetrix Corporation
    Inventors: Koji Arita, Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Patent number: 6306667
    Abstract: In a method for forming a capacitor in the semiconductor memory, a lower electrode is formed on an interlayer insulator film, and a high dielectric constant insulating film is formed to cover the whole surface including the lower electrode. Furthermore, an upper electrode layer is formed to cover the high dielectric constant insulating film. Thereafter, a plasma treatment is carried out to expose a surface of the upper electrode layer to plasma so that a suctorial layer is uniformly formed at the whole surface of the upper electrode layer, and then, a NSG film is grown on the whole surface of the upper electrode layer by a CVD process using TEOS as a starting material. Thus, an interlayer insulator film of the NSG film can be formed to have a uniform film thickness over the whole surface of the upper electrode.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: October 23, 2001
    Assignee: NEC Corporation
    Inventors: Koji Arita, Yoshitake Kato
  • Publication number: 20010031505
    Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.
    Type: Application
    Filed: May 19, 2001
    Publication date: October 18, 2001
    Applicant: Symetrix Corporation and Matsushita Electronics Corporation
    Inventors: Koji Arita, Shinichiro Hayashi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Patent number: 6294438
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: September 25, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6291290
    Abstract: A method of making a top electrode for a thin film capacitor with a multi-layer structure that includes a high dielectric oxide layer, a first conductive layer on the high dielectric oxide layer and having a high formability to a reactive ion etching, and a second conductive layer on the first conductive layer, the second conductive layer having a high formability to the reactive ion etching. The first conductive layer is deposited with a lower deposition rate than the second conductive layer. An interface between the first conductive layer and the high dielectric oxide layer is such that a density of a leak current across the interface is suppressed at not higher than 1×10−8 A/cm2 upon applying a voltage of 2V across the dielectric oxide layer after the multi-layer structure has been subjected to a heat treatment at 350° C.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: September 18, 2001
    Assignee: NEC Corporation
    Inventor: Koji Arita
  • Publication number: 20010019874
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Application
    Filed: January 24, 2001
    Publication date: September 6, 2001
    Applicant: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Publication number: 20010019497
    Abstract: Data is read out from a ferroelectric film with its remnant polarization associated with one of two possible logical states of the data and with a bias voltage applied to a control gate electrode over the ferroelectric film. The ferroelectric film creates either up or down remnant polarization. So the down remnant polarization may represent data “1” while the up or almost zero remnant polarization may represent data “0”, for example. By regarding the almost zero remnant polarization state as representing data “0”, a read current value becomes substantially constant in the data “0” state. As a result, the read accuracy improves. Also, if imprinting of one particular logical state (e.g., data “1”) is induced in advance, then the read accuracy further improves.
    Type: Application
    Filed: February 14, 2001
    Publication date: September 6, 2001
    Inventors: Yasuhiro Shimada, Koji Arita, Kiyoshi Uchiyama
  • Patent number: 6281534
    Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75° C., and after 109 negative polarization switching pulses at 125° C.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: August 28, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Koji Arita, Shinichiro Hayashi, Joseph D. Cuchiaro, Carlos A. Paz de Araujo
  • Publication number: 20010011743
    Abstract: A nonvolatile nondestructible read-out ferroelectric FET memory comprising a semiconductor substrate, a ferroelectric functional gradient material (“FGM”) thin film, and a gate electrode. In one basic embodiment, the ferroelectric FGM thin film contains a ferroelectric compound and a dielectric compound. The dielectric compound has a lower dielectric constant than the ferroelectric compound. There is a concentration gradient of the ferroelectric compound in the thin film. In a second basic embodiment, the FGM thin film is a functional gradient ferroelectric (“FGF”), in which compositional gradients of ferroelectric compounds result in unconventional hysteresis behavior. The unconventional hysteresis behavior of FGF thin films is related to an enlarged memory window in ferroelectric FET memories. FGM thin films are preferably formed using a liquid source MOD methods, preferably a multisource CVD method.
    Type: Application
    Filed: February 27, 2001
    Publication date: August 9, 2001
    Applicant: Symetrix Corporation
    Inventors: Koji Arita, Carlos A. Paz de Araujo
  • Patent number: 6255121
    Abstract: A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1-xZrx)O2, wherein 0≦x≦1.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: July 3, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Koji Arita, Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Patent number: 6236076
    Abstract: A nonvolatile nondestructible read-out ferroelectric FET memory comprising a semiconductor substrate, a ferroelectric functional gradient material (“FGM”) thin film, and a gate electrode. In one basic embodiment, the ferroelectric FGM thin film contains a ferroelectric compound and a dielectric compound. The dielectric compound has a lower dielectric constant than the ferroelectric compound. There is a concentration gradient of the ferroelectric compound in the thin film. In a second basic embodiment, the FGM thin film is a functional gradient ferroelectric (“FGF”), in which compositional gradients of ferroelectric compounds result in unconventional hysteresis behavior. The unconventional hysteresis behavior of FGF thin films is elated to an enlarged memory window in ferroelectric FET memories. FGM thin films are preferably formed using a liquid source MOD methods, preferably a multisource CVD method.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: May 22, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Koji Arita, Carlos A. Paz de Araujo
  • Patent number: 6214660
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: April 10, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eigi Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6204111
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: March 20, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6198225
    Abstract: A thin film of ferroelectric layered superlattice material in a flat panel display device is energized to selectively influence the display image. In one embodiment, a voltage pulse causes the layered superlattice material to emit electrons that impinge upon a phosphor, causing the phosphor to emit light. In another embodiment, an electric potential creates a remanent polarization in the layered superlattice material, which exerts an electric field in liquid crystal layer, thereby influencing the transmissivity of light through the liquid crystal. The layered superlattice material is a metal oxide formed using an inventive liquid precursor containing an alkoxycarboxylate. The thin film thickness is preferably in the range 50-140 nm, so that polarizabilty and transparency of the thin film is enhanced. A display element may comprise a varistor device to prevent cross-talk between pixels and to enable sudden polarization switching. A functional gradient in the ferroelectric thin film enhances electron emission.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: March 6, 2001
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Gota Kano, Yasuhiro Shimada, Shinichiro Hayashi, Koji Arita, Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Larry D. McMillan
  • Patent number: 6169304
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6143597
    Abstract: A method of manufacturing a capacitor comprises a step of forming a first dielectric layer composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode, a step of sintering the first dielectric layer, a step of forming a second dielectric layer on the first dielectric layer, and a step of forming a second electrode on the second dielectric layer. By forming the second dielectric layer having small crystal grain size on the first dielectric layer having large crystal grain size, the surface of the capacitor insulating layer becomes flat.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: November 7, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Akihiro Matsuda, Yoshihisa Nagano, Toru Nasu, Koji Arita, Yasuhiro Uemoto
  • Patent number: 6140672
    Abstract: A ferroelectric non-volatile memory in which each memory cell consists of a metal-ferroelectric-metal ("MFM") capacitor and a FET on a semiconductor substrate. The MFM and the FET are separated by an interlayer dielectric layer. A local interconnect connects the gate electrode of the FET to the bottom electrode of the MFM capacitor. Preferably, the MFM is located directly above the gate electrode, and the local interconnect is a conductive plug in a filled via. Preferably, the ferroelectric thin film of the MFM comprises a layered superlattice material. Preferably, a dielectric metal oxide insulator layer is located between the gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: October 31, 2000
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Koji Arita, Carlos A. Paz de Araujo
  • Patent number: 6107657
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: August 22, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki