Patents by Inventor Koji Asakawa

Koji Asakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9153363
    Abstract: The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eishi Tsutsumi, Tsutomu Nakanishi, Akira Fujimoto, Koji Asakawa
  • Patent number: 9142562
    Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating film; an organic molecular layer, which is formed between the semiconductor layer and the block insulating film, and provided with a first organic molecular film on the semiconductor layer side containing first organic molecules and a second organic molecular film on the block insulating film side containing second organic molecules, and in which the first organic molecule has a charge storing unit and the second organic molecule is an amphiphilic organic molecule; and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: September 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Hattori, Masaya Terai, Hideyuki Nishizawa, Koji Asakawa, Yoshiaki Fukuzumi
  • Patent number: 9142728
    Abstract: According to one embodiment, a semiconductor light emitting device includes a structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes an electrode layer provided on the second semiconductor layer side of the structure. The electrode layer includes a metal portion with a thickness of not less than 10 nanometers and not more than 100 nanometers. A plurality of openings pierces the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers. The device includes an inorganic film providing on the metal portion and inner surfaces of the openings, the inorganic film having transmittivity with respect to light emitted from the light emitting layer.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: September 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Kumi Masunaga, Kenji Nakamura, Tsutomu Nakanishi, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani
  • Publication number: 20150263125
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer, a control gate electrode, and an organic molecular layer provided between the semiconductor layer and the control gate electrode and having an organic molecule including a porphyrin structure with oxymetal or chlorometal at the center.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaya TERAI, Tsukasa TADA, Hideyuki NISHIZAWA, Shigeki HATTORI, Koji ASAKAWA
  • Publication number: 20150261092
    Abstract: According to one embodiment, there is provided a method of forming a pattern, including forming a thermally crosslinkable molecule layer including a thermally crosslinkable molecule on a substrate, forming a photosensitive composition layer including a photosensitive composition on the thermally crosslinkable molecule layer, chemically binding the thermally crosslinkable molecule to the photosensitive composition by heating, selectively irradiating the photosensitive composition layer with energy rays, forming a block copolymer layer including a block copolymer on the photosensitive composition layer, and forming a microphase-separated structure in the block copolymer layer.
    Type: Application
    Filed: June 1, 2015
    Publication date: September 17, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi HIENO, Shigeki HATTORI, Hiroko NAKAMURA, Satoshi MlKOSHIBA, Koji ASAKAWA, Masahiro KANNO, Yuriko SEINO, Tsukasa AZUMA
  • Publication number: 20150263127
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer, a control gate electrode, and an organic molecular layer provided between the semiconductor layer and the control gate electrode and having an organic molecule including a porphyrin structure.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeki HATTORI, Masaya TERAI, Hideyuki NISHIZAWA, Koji ASAKAWA, Yoshiaki FUKUZUMI
  • Patent number: 9136405
    Abstract: The present invention provides a light transmission type solar cell excellent in both power generation efficiency and light transparency, and also provides a method for producing that solar cell. The solar cell of the present invention comprises a photoelectric conversion layer, a light-incident side electrode layer, and a counter electrode layer. The incident side electrode layer is provided with plural openings bored through the layer, and has a thickness of 10 nm to 200 nm. Each of the openings occupies an area of 80 nm2 to 0.8 ?m2, and the opening ratio is in the range of 10% to 66%. The transmittance of the whole cell is 5% or more at 700 nm wavelength. The incident side electrode layer can be formed by etching fabrication with a stamper. In the etching fabrication, a mono-particle layer of fine particles or a dot pattern formed by self-assembled block copolymer can be used as a mask.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: September 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eishi Tsutsumi, Kumi Masunaga, Ryota Kitagawa, Tsutomu Nakanishi, Akira Fujimoto, Hideyuki Nishizawa, Koji Asakawa
  • Publication number: 20150236171
    Abstract: An organic molecular memory of an embodiment includes a first conductive layer, a second conductive layer, and an organic molecular layer interposed between the first conductive layer and the second conductive layer, the organic molecular layer including variable-resistance molecular chains or charge-storage molecular chains, the variable-resistance molecular chains or the charge-storage molecular chains having electron-withdrawing substituents.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki NISHIZAWA, Shigeki Hattori, Masaya Terai, Satoshi Mikoshiba, Koji Asakawa, Tsukasa Tada
  • Publication number: 20150228335
    Abstract: An organic molecular memory of an embodiment includes a first conductive layer, a second conductive layer, and an organic molecular layer interposed between the first conductive layer and the second conductive layer, the organic molecular layer including charge-storage molecular chains or variable-resistance molecular chains, the charge-storage molecular chains or the variable-resistance molecular chains including fused polycyclic groups.
    Type: Application
    Filed: April 24, 2015
    Publication date: August 13, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideyuki NISHIZAWA, Reiko YOSHIMURA, Tsukasa TADA, Shigeki HATTORI, Masaya TERAI, Satoshi MIKOSHIBA, Koji ASAKAWA
  • Patent number: 9073284
    Abstract: According to one embodiment, there is provided a method of forming a pattern, including forming a thermally crosslinkable molecule layer including a thermally crosslinkable molecule on a substrate, forming a photosensitive composition layer including a photosensitive composition on the thermally crosslinkable molecule layer, chemically binding the thermally crosslinkable molecule to the photosensitive composition by heating, selectively irradiating the photosensitive composition layer with energy rays, forming a block copolymer layer including a block copolymer on the photosensitive composition layer, and forming a microphase-separated structure in the block copolymer layer.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: July 7, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Hieno, Shigeki Hattori, Hiroko Nakamura, Satoshi Mikoshiba, Koji Asakawa, Masahiro Kanno, Yuriko Seino, Tsukasa Azuma
  • Patent number: 9054324
    Abstract: An organic molecular memory of an embodiment includes a first conductive layer, a second conductive layer, and an organic molecular layer interposed between the first conductive layer and the second conductive layer, the organic molecular layer including variable-resistance molecular chains or charge-storage molecular chains, the variable-resistance molecular chains or the charge-storage molecular chains having electron-withdrawing substituents.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Nishizawa, Shigeki Hattori, Masaya Terai, Satoshi Mikoshiba, Koji Asakawa, Tsukasa Tada
  • Patent number: 9047941
    Abstract: An organic molecular memory of an embodiment includes a first conductive layer, a second conductive layer, and an organic molecular layer interposed between the first conductive layer and the second conductive layer, the organic molecular layer including charge-storage molecular chains or variable-resistance molecular chains, the charge-storage molecular chains or the variable-resistance molecular chains including fused polycyclic groups.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: June 2, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Nishizawa, Reiko Yoshimura, Tsukasa Tada, Shigeki Hattori, Masaya Terai, Satoshi Mikoshiba, Koji Asakawa
  • Patent number: 9040324
    Abstract: A semiconductor light-emitting device according to the embodiment includes a substrate, a compound semiconductor layer, a metal electrode layer provided with particular openings, a light-extraction layer, and a counter electrode. The light-extraction layer has a thickness of 20 to 120 nm and covers at least partly the metal part of the metal electrode layer; or otherwise the light-extraction layer has a rugged structure and covers at least partly the metal part of the metal electrode layer. The rugged structure has projections so arranged that their summits are positioned at intervals of 100 to 600 nm, and the heights of the summits from the surface of the metal electrode layer are 200 to 700 nm.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Ryota Kitagawa, Eishi Tsutsumi, Koji Asakawa
  • Patent number: 9013150
    Abstract: Provided is a power supply device integrally combined with an electrical device body including a motor, comprising a rechargeable battery for supplying power to the motor, a microcomputer for detecting a residual capacity and a battery voltage of the battery, and a switching element provided between the battery and the microcomputer. The microcomputer stops charging the battery when the detected residual capacity has become 100%, and when the detected value of the battery voltage has become lower than a peak value after the value of the battery voltage passes the peak value, making it possible to prevent overcharging of the battery. The microcomputer also controls to turn off the switching element to stop the power supply from the battery to the microcomputer when the residual capacity becomes less than a predetermined threshold value, making it possible to reduce power consumption.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kazunori Watanabe, Koji Asakawa
  • Patent number: 9000504
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Hattori, Reika Ichihara, Masaya Terai, Hideyuki Nishizawa, Tsukasa Tada, Koji Asakawa, Hiroyuki Fuke, Satoshi Mikoshiba, Yoshiaki Fukuzumi, Hideaki Aochi
  • Patent number: 8993869
    Abstract: A photoelectric conversion element includes a photoelectric conversion layer to include a first metal layer, a semiconductor layer, and a second metal layer, all of which are laminated. In addition, at least one of the first metal layer and the second metal layer is a nano-mesh metal having a plurality of through holes or a dot metal having a plurality of metal dots arranged separately from each other on the semiconductor layer. The photoelectric conversion layer includes a long-wavelength absorption layer containing an impurity which is different from impurities for p-type doping and n-type doping of the semiconductor layer. The long-wavelength absorption layer is within a depth of 5 nm from the nano-mesh metal or the dot metal.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Tsutomu Nakanishi, Kenji Nakamura, Kumi Masunaga, Koji Asakawa
  • Publication number: 20150083988
    Abstract: An organic molecular memory in an embodiment includes a first conducive layer, a second conductive layer, and an organic molecular layer provided between the first conductive layer and the second conductive layer, the organic molecular layer having an organic molecule, the organic molecule having a linker group bonded to the first conductive layer, a ? conjugated chain bonded to the linker group, and a phenyl group bonded to the ? conjugated chain opposite to the linker group and facing the second conductive layer, the ? conjugated chain including electron-accepting groups or electron-donating groups arranged in line asymmetry with respect to a bonding direction of the ? conjugated chain, the phenyl group having substituents R0, R1, R2, R3, and R4 as shown in the following formula, the substituent R0 being an electron-accepting group or an electron-donating group.
    Type: Application
    Filed: August 11, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke TANAKA, Hideyuki Nishizawa, Shigeki Hattori, Koji Asakawa
  • Patent number: 8986488
    Abstract: According to one embodiment, a pattern formation method is provided, the pattern formation includes: laminating a self-assembled monolayer and a polymer film on a substrate; causing chemical bonding between the polymer film and the self-assembled monolayer by irradiation with an energy beam to form a polymer surface layer on the self-assembled monolayer; and forming on the polymer surface layer a polymer alloy having a pattern of phase-separated structures.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Hattori, Koji Asakawa, Hiroko Nakamura, Ryota Kitagawa, Yuriko Seino, Masahiro Kanno, Momoka Higa
  • Publication number: 20150069337
    Abstract: An organic molecular device of an embodiment includes a first and a second conductive layers and an organic molecular layer having an organic molecule provided between the first and the second conductive layer. The organic molecule includes a one-dimensional or quasi one-dimensional ?-conjugated system chain having either a first aromatic ring or a second aromatic ring. The first aromatic ring has one or more substituents that are an electron withdrawing group, each substituent of the first aromatic ring is independently selected from the group consisting of the electron withdrawing group and hydrogen, the second aromatic ring has one or more substituents that are an electron releasing group, and each substituent of the second aromatic ring is independently selected from the group consisting of the electron releasing group and hydrogen. The first aromatic ring or the second aromatic ring exist in an unbalanced manner in the ?-conjugated system chain.
    Type: Application
    Filed: March 4, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki NISHIZAWA, Shigeki HATTORI, Yusuke TANAKA, Koji ASAKAWA
  • Publication number: 20150072456
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer.
    Type: Application
    Filed: November 18, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kumi MASUNAGA, Ryota Kitagawa, Akira Fujimoto, Koji Asakawa, Takanobu Kamakura, Shinji Nunotani