Patents by Inventor Koji Dairiki

Koji Dairiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8618544
    Abstract: To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Takayuki Ikeda, Hidekazu Miyairi, Yoshiyuki Kurokawa, Hiromichi Godo, Daisuke Kawae, Takayuki Inoue, Satoshi Kobayashi
  • Publication number: 20130323912
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Application
    Filed: July 25, 2013
    Publication date: December 5, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko TAMURA, Eiji SUGIYAMA, Yoshitaka DOZEN, Koji DAIRIKI, Takuya TSURUME
  • Publication number: 20130313555
    Abstract: A photoelectric conversion element including a first gate electrode, a first gate insulating layer, a crystalline semiconductor layer, an amorphous semiconductor layer, an impurity semiconductor layer, a source electrode and a drain electrode in contact with the impurity semiconductor layer, a second gate insulating layer covering a region between the source electrode and the drain electrode, and a second gate electrode over the second gate insulating layer. In the photoelectric conversion element, a light-receiving portion is provided in the region between the source electrode and the drain electrode, the first gate electrode includes a light-shielding material and overlaps with the entire surface of the crystalline semiconductor layer and the amorphous semiconductor layer, the second gate electrode includes a light-transmitting material and overlaps with the light-receiving portion, and the first gate electrode is electrically connected to the source electrode or the drain electrode is provided.
    Type: Application
    Filed: August 6, 2013
    Publication date: November 28, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsudoi NAGI, Koji Dairiki
  • Patent number: 8530335
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen, Koji Dairiki, Takuya Tsurume
  • Patent number: 8519394
    Abstract: In an inverted staggered thin film transistor, a microcrystalline silicon film and a silicon carbide film are provided between a gate insulating film and wirings serving as a source wiring and a drain wiring. The microcrystalline silicon film is formed on the gate insulating film side and the silicon carbide film is formed on the wiring side. In such a manner, a semiconductor device having favorable electric characteristics can be manufactured with high productivity.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Koji Dairiki, Satoshi Toriumi
  • Patent number: 8519397
    Abstract: A photoelectric conversion element including a first gate electrode, a first gate insulating layer, a crystalline semiconductor layer, an amorphous semiconductor layer, an impurity semiconductor layer, a source electrode and a drain electrode in contact with the impurity semiconductor layer, a second gate insulating layer covering a region between the source electrode and the drain electrode, and a second gate electrode over the second gate insulating layer. In the photoelectric conversion element, a light-receiving portion is provided in the region between the source electrode and the drain electrode, the first gate electrode includes a light-shielding material and overlaps with the entire surface of the crystalline semiconductor layer and the amorphous semiconductor layer, the second gate electrode includes a light-transmitting material and overlaps with the light-receiving portion, and the first gate electrode is electrically connected to the source electrode or the drain electrode is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsudoi Nagi, Koji Dairiki
  • Patent number: 8513664
    Abstract: A thin film transistor includes, as a buffer layer, an amorphous semiconductor layer having nitrogen or an NH group between a gate insulating layer and source and drain regions and at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshiyuki Isa, Yasuhiro Jinbo, Sachiaki Tezuka, Koji Dairiki, Hidekazu Miyairi, Shunpei Yamazaki
  • Patent number: 8507313
    Abstract: A fragile layer is formed in a region at a depth of less than 1000 nm from one surface of a single crystal semiconductor substrate, and a first impurity semiconductor layer and a first electrode are formed at the one surface side. After bonding the first electrode and a supporting substrate, the single crystal semiconductor substrate is separated using the fragile layer or the vicinity as a separation plane, thereby forming a first single crystal semiconductor layer over the supporting substrate. An amorphous semiconductor layer is formed on the first single crystal semiconductor layer, and a second single crystal semiconductor layer is formed by heat treatment for solid phase growth of the amorphous semiconductor layer. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer and a second electrode are formed over the second single crystal semiconductor layer.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: August 13, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumito Isaka, Sho Kato, Koji Dairiki
  • Patent number: 8492246
    Abstract: It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Naoto Kusumoto, Takuya Tsurume
  • Patent number: 8487306
    Abstract: A photoelectric conversion element includes a first conductive layer over a substrate; a first insulating layer covering the first conductive layer; a first semiconductor layer over the first insulating layer; a second conductive layer formed over the first semiconductor layer; an impurity semiconductor layer over the second semiconductor layer; a second conductive layer over the impurity semiconductor layer; a second insulating layer covering the first semiconductor layer and the second conductive layer; and a light-transmitting third conductive layer over the second insulating layer. A first opening and a second opening are formed in the second insulating layer. In the first opening, the first semiconductor layer is connected to the third conductive layer. In the second opening, the first conductive layer is connected to the third conductive layer. In the first opening, a light-receiving portion surrounded by an electrode formed of the second conductive layer is provided.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Hidekazu Miyairi, Tsudoi Nagi
  • Patent number: 8426293
    Abstract: It is an object of the present invention to decrease a unit cost of an IC chip and to achieve the mass-production of IC chips. According to the present invention, a substrate having no limitation in size, such as a glass substrate, is used instead of a silicon substrate. This achieves the mass-production and the decrease of the unit cost of the IC chip. Further, a thin IC chip is provided by grinding and polishing the substrate such as the glass substrate.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Koji Dairiki, Naoto Kusumoto
  • Patent number: 8389993
    Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Kobayashi, Ikuko Kawamata, Koji Dairiki, Shigeki Komori, Toshiyuki Isa, Shunpei Yamazaki
  • Patent number: 8384081
    Abstract: The present invention is to provide a semiconductor device that achieves high mechanical strength without reducing the circuit scale and that can prevent the data from being forged and altered illegally while suppressing the cost. The present invention discloses a semiconductor device typified by an ID chip that is formed from a semiconductor thin film including a first region with high crystallinity and a second region with the crystallinity inferior to the first region. Specifically, a TFT (thin film transistor) of a circuit requiring high-speed operation is formed by using the first region and a memory element for an identifying ROM is formed by using the second region.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koji Dairiki
  • Patent number: 8361845
    Abstract: An object is to provide a method for manufacturing a semiconductor device which suppresses an influence on a semiconductor element due to entry of an impurity element, moisture, or the like from outside even in the case of thinning or removing a substrate after forming a semiconductor element over the substrate. A feature is to form an insulating film functioning as a protective film on at least one side of the substrate by performing surface treatment on the substrate, to form a semiconductor element such as a thin film transistor over the insulating film, and to thin the substrate. As the surface treatment, addition of an impurity element or plasma treatment is performed on the substrate. As a means for thinning the substrate, the substrate can be partially removed by performing grinding treatment, polishing treatment, or the like on the other side of the substrate.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Naoto Kusumoto, Takuya Tsurume
  • Patent number: 8343858
    Abstract: A method for manufacturing a microcrystalline semiconductor film having high crystallinity is provided. A method for manufacturing a semiconductor device which has favorable electric characteristics with high productivity is provided. After a first microcrystalline semiconductor film is formed over a substrate, treatment for flattening a surface of the first microcrystalline semiconductor film is performed. Then, treatment for removing an amorphous semiconductor region on a surface side of the flattened first microcrystalline semiconductor film is performed so that a second microcrystalline semiconductor film having high crystallinity and flatness is formed. After that, a third microcrystalline semiconductor film is formed over the second microcrystalline semiconductor film.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Tomokazu Yokoi, Koji Dairiki
  • Publication number: 20120322212
    Abstract: It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.
    Type: Application
    Filed: August 28, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Koji DAIRIKI, Junya MARUYAMA, Tomoko TAMURA, Eiji SUGIYAMA, Yoshitaka DOZEN
  • Publication number: 20120298997
    Abstract: One embodiment of the present invention is a semiconductor device which includes a gate electrode; a gate insulating film formed to cover the gate electrode; a semiconductor layer formed over the gate insulating film and placed above the gate electrode; a second insulating film formed over the semiconductor layer; a first insulating film formed over a top surface and a side surface of the second insulating film, a side surface of the semiconductor layer, and the gate insulating film; silicon layers and which are formed over the first insulating film and electrically connected to the semiconductor layer; and a source electrode and a drain electrode which are formed over the silicon layers. The source electrode and the drain electrode are electrically separated from each other over the first insulating film. The semiconductor layer is not in contact with each of the source electrode and the drain electrode.
    Type: Application
    Filed: May 17, 2012
    Publication date: November 29, 2012
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu MIYAIRI, Koji DAIRIKI, Yasuhiro JINBO, Tomohiro KIMURA, Yoshitaka YAMAMOTO
  • Publication number: 20120298999
    Abstract: An object is to reduce off-state leakage current between a source electrode and a drain electrode. One embodiment of the present invention is a semiconductor device including a gate electrode, gate insulating films and formed to cover the gate electrode, an active layer formed over the gate insulating films and located above the gate electrode, silicon layers and formed over side surfaces of the active layer and the gate insulating films, and a source electrode and a drain electrode formed over the silicon layers. The active layer is not in contact with each of the source electrode and the drain electrode.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yasuhiro JINBO, Koji DAIRIKI, Hidekazu MIYAIRI, Tomohiro KIMURA, Yoshitaka YAMAMOTO
  • Patent number: 8288773
    Abstract: It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Junya Maruyama, Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen
  • Patent number: 8263421
    Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: September 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara