Patents by Inventor Koji Matsui

Koji Matsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7338884
    Abstract: An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: March 4, 2008
    Assignee: NEC Corporation
    Inventors: Tadanori Shimoto, Katsumi Kikuchi, Koji Matsui, Kazuhiro Baba
  • Publication number: 20080026240
    Abstract: An Sn—Zn alloy solder having a composition comprising 7 to 10 mass % of Zn, 0.075 to 1 mass % of Ag, and 0.07 to 0.5 mass % of Al; further comprising one or two components selected from 0.01 to 6 mass % of Bi and 0.007 to 0.1 mass % of Cu; and optionally comprising 0.007 to 0.1 mass %, with the balance being Sn and unavoidable impurities. The solder has the same processability, service conditions, and connection reliability as conventional Sn-37 mass % Pb eutectic solder, and does not contain the biologically harmful lead.
    Type: Application
    Filed: April 21, 2005
    Publication date: January 31, 2008
    Inventors: Takuo Funaya, Osamu Myohga, Koji Matsui
  • Patent number: 7266669
    Abstract: The storage area of a storage unit includes a file area and temporary write area. A pair of map tables are allocated in the storage area. An update processing unit executes update of a page in a file stored in a file area by writing updated data to an unused page acquired from a temporary write area. A commit module alternately writes a list of effective pages in the temporary write area to the pair of map tables whenever each of transactions is committed. A checkpoint processing unit writes back the updated data of each effective page in the temporary write area to the corresponding original page position in the file area.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: September 4, 2007
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventors: Koji Matsui, Hitoshi Tanigawa, Yuji Kondo
  • Publication number: 20060244137
    Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.
    Type: Application
    Filed: June 29, 2006
    Publication date: November 2, 2006
    Inventors: Katsumi Kikuchi, Tadanori Shimoto, Koji Matsui, Kazuhiro Baba
  • Publication number: 20060103028
    Abstract: An object of the present invention is to provide an electronic part device which can be repaired even in the case of an electronic part device having a malfunction in electrical connection after carrying out underfill. The present invention is an electronic part device in which a semiconductor element (flip chip) (3) is mounted on a wiring circuit substrate (1) under such a state that an electrode part for connection (joint ball) disposed on the semiconductor element (flip chip) (3) and a circuit electrode (5) disposed on the wiring circuit substrate (1) are facing with each other. In addition, the gap between the wiring circuit substrate (1) and the semiconductor element (flip chip) (3) is filled by a filling resin layer (4) comprising a liquid epoxy resin composition which comprises the following component (D) and the following components (A) to (C) (A) A liquid epoxy resin. (B) A curing agent. (C) An N,N,N?,N?-tetra-substituted fluorine-containing aromatic diamine compound.
    Type: Application
    Filed: December 24, 2003
    Publication date: May 18, 2006
    Applicants: NITTO DENKO CORPORATION, NEC CORPORATION
    Inventors: Ichiro Hazeyama, Masahiro Kubo, Sakae Kitajo, Koji Matsui, Kazumasa Igarashi, Hiroshi Noro
  • Publication number: 20060069885
    Abstract: The storage area of a storage unit includes a file area and temporary write area. A pair of map tables are allocated in the storage area. An update processing unit executes update of a page in a file stored in a file area by writing updated data to an unused page acquired from a temporary write area. A commit module alternately writes a list of effective pages in the temporary write area to the pair of map tables whenever each of transactions is committed. A checkpoint processing unit writes back the updated data of each effective page in the temporary write area to the corresponding original page position in the file area.
    Type: Application
    Filed: June 6, 2005
    Publication date: March 30, 2006
    Inventors: Koji Matsui, Hitoshi Tanigawa, Yuji Kondo
  • Publication number: 20050130413
    Abstract: An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 16, 2005
    Applicant: NEC CORPORATION
    Inventors: Tadanori Shimoto, Katsumi Kikuchi, Koji Matsui, Kazuhiro Baba
  • Publication number: 20050098875
    Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.
    Type: Application
    Filed: December 3, 2004
    Publication date: May 12, 2005
    Inventors: Katsumi Kikuchi, Tadanori Shimoto, Koji Matsui, Kazuhiro Baba
  • Patent number: 6861757
    Abstract: An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: March 1, 2005
    Assignee: NEC Corporation
    Inventors: Tadanori Shimoto, Katsumi Kikuchi, Koji Matsui, Kazuhiro Baba
  • Patent number: 6841862
    Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: January 11, 2005
    Assignee: NEC Corporation
    Inventors: Katsumi Kikuchi, Tadanori Shimoto, Koji Matsui, Kazuhiro Baba
  • Patent number: 6798070
    Abstract: An electronic device assembly for dense mounting of electronic devices and method of connecting the electronic devices are disclosed. Conductive portions implemented by metal bumps and sealing portions implemented by adhesive seal resin are connected by thermocompression at the same time between two electronic devices. This may be repeated between three or more electronic device.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: September 28, 2004
    Assignee: NEC Corporation
    Inventors: Takuo Funaya, Tadanori Shimoto, Naoji Senba, Koji Matsui
  • Patent number: 6674016
    Abstract: An electronic component is described, which contains a printed circuit board having electrodes for connection and a semiconductor chip having electrodes for connection which is mounted on said circuit board with their electrodes facing those of the circuit board, the gap between the circuit board and the semiconductor chip being filled with a sealing resin layer, wherein the sealing resin layer is formed of a liquid epoxy resin composition containing (A) a liquid epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) an N,N,N′,N′-tetrasubstituted fluorine-containing aromatic diamine derivative.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: January 6, 2004
    Assignees: Nitto Denko Corporation, NEC Corporation
    Inventors: Masahiro Kubo, Ichiro Hazeyama, Sakae Kitajo, Koji Matsui, Kazumasa Igarashi
  • Publication number: 20030116347
    Abstract: An electronic component is described, which contains a printed circuit board having electrodes for connection and a semiconductor chip having electrodes for connection which is mounted on said circuit board with their electrodes facing those of the circuit board, the gap between the circuit board and the semiconductor chip being filled with a sealing resin layer, wherein the sealing resin layer is formed of a liquid epoxy resin composition containing (A) a liquid epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) an N,N,N′,N′-tetrasubstituted fluorine-containing aromatic diamine derivative.
    Type: Application
    Filed: September 19, 2002
    Publication date: June 26, 2003
    Applicants: NITTO DENKO CORPORATION, NEC CORPORATION
    Inventors: Masahiro Kubo, Ichiro Hazeyama, Sakae Kitajo, Koji Matsui, Kazumasa Igarashi
  • Patent number: 6576499
    Abstract: An electronic device assembly for dense mounting of electronic devices and method of connecting the electronic devices are disclosed. Conductive portions implemented by metal bumps and sealing portions implemented by adhesive seal resin are connected by thermocompression at the same time between two electronic devices. This may be repeated between three or more electronic device.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: June 10, 2003
    Assignee: NEC Corporation
    Inventors: Takuo Funaya, Tadanori Shimoto, Naoji Senba, Koji Matsui
  • Publication number: 20030064147
    Abstract: A method for manufacturing a flexible printed circuit in which a resin solution is applied onto a circuit substrate having a wiring pattern on its surface so as to form a resin cover layer, having the steps of: wetting the surface of the circuit substrate with a solvent which is capable of dissolving the resin; applying the resin solution onto the surface wetted with the solvent; and drying the resin solution to thereby form the resin cover layer. A flexible printed circuit obtained in the manufacturing method.
    Type: Application
    Filed: September 24, 2002
    Publication date: April 3, 2003
    Applicant: NITTO DENKO CORPORATION
    Inventors: Hirofumi Fujii, Koji Matsui, Hideaki Taki, Shunichi Hayashi, Makoto Saito
  • Publication number: 20030045024
    Abstract: An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.
    Type: Application
    Filed: March 15, 2002
    Publication date: March 6, 2003
    Inventors: Tadanori Shimoto, Katsumi Kikuchi, Koji Matsui, Kazuhiro Baba
  • Patent number: 6515869
    Abstract: A supporting substrate for mounting a semiconductor bare chip thereon has a surface provided with electrode pads thereon and bumps on the electrode pads. A sealing resin film is selectivley formed on the periphery of the surface of the supporting substrate, except over the bumps, and further the sealing resin film has at least a thermosetting property. The electrode pads of the supporting substrate and the bumps of the semiconductor bare chip are bonded by a thermo-compression bonding.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: February 4, 2003
    Assignee: NEC Corporation
    Inventors: Takuo Funaya, Koji Matsui
  • Patent number: 6466124
    Abstract: There is provided a thin film resistor formed of titanium nitride containing oxygen in a solid solution condition.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: October 15, 2002
    Assignee: NEC Corporation
    Inventors: Akinobu Shibuya, Koji Matsui
  • Patent number: 6444403
    Abstract: A method of making a multilayer buildup printed circuit board and mounting substrate wherein a resin laminated wiring sheet, which has a copper foil, an epoxy-acrylate photosensitive resin composition having a fluorene structure, and a conductive pattern, are overlaid on the conductive pattern side of a supporting substrate at 100° C. and 3 kg/cm2, and adhered thereto at 200 to 300° C. and 10 kg/cm2. The copper foil is entirely etched by wet-etching or is etched into a predetermined pattern so as to form a wiring structure. Since the epoxy-acrylate photosensitive resin composition is not treated at 100° C. or more, and hence is in a semi-cured state, the epoxy-acrylate photosensitive resin composition can be heat-bonded onto the supporting substrate.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: September 3, 2002
    Assignees: NEC Corporation, Nippon Steel Chemical Co., Ltd.
    Inventors: Tadanori Shimoto, Koji Matsui, Takero Teramoto, Hironobu Kawasato
  • Publication number: 20020092610
    Abstract: A supporting substrate for mounting a semiconductor bare chip thereon has a surface provided with electrode pads thereon and bumps on the electrode pads. A sealing resin film is selectively formed on the surface of the supporting substrate, except cover the bumps, and further the sealing resin film has at least a thermosetting property. The electrode pads of the above supporting substrate and the bumps of the semiconductor bare chip are bonded by a thermo-compression bonding method whereby the sealing between the supporting substrate and the semiconductor bare chip is simultaneously conducted.
    Type: Application
    Filed: March 6, 2000
    Publication date: July 18, 2002
    Inventors: TAKUO FUNAYA, KOJI MATSUI