Patents by Inventor Koji Miyata

Koji Miyata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10319979
    Abstract: A battery includes a power generation component including a positive electrode, a negative electrode, and an electrolyte, and a battery case accommodating the power generation component. The negative electrode includes a first lead (17) having a single layer structure whose main component is nickel, and a second lead (18) having a layered structure including a Ni layer (18a) whose main component is nickel and a Cu layer (18b) whose main component is copper. The battery includes a layered portion (35) formed of the leads that are superposed such that the Ni layer (18a) of the second lead (18) faces the first lead (17). Part of the layered portion (35) is welded to an inner surface of the battery case with the first lead (17) at the layered portion (35) being disposed on a battery case side.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: June 11, 2019
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Shin Haraguchi, Kyosuke Miyata, Koji Funami
  • Publication number: 20190090565
    Abstract: Provided is an artificial hair fiber which can prevent detachment between core and sheath, having superior texture close to human hair, and having superior curl retention. An artificial hair fiber has a core-sheath structure, including: a core; and a sheath covering the core; and: the core includes a core resin composition including polyester; the sheath includes a sheath resin composition including polyamide; the core and the sheath have a core/sheath mass ratio of 40/60 to 90/10; and when a melt viscosity of the polyester of the core is expressed as a, and a melt viscosity of the polyamide of the sheath is expressed as b, a viscosity ratio a/b is 0.5 to 2.5.
    Type: Application
    Filed: March 21, 2017
    Publication date: March 28, 2019
    Applicant: DENKA COMPANY LIMITED
    Inventors: Koji Miyata, Atsushi Horihata, Kazuhito Sonoda, Atsushi Takei
  • Publication number: 20190079597
    Abstract: A method includes identifying a first area in a real space. The method further includes identifying in a virtual space a second area corresponding to the first area. The method further includes detecting in the first area a first position of a part of a body of a user. The method further includes moving, in the second area, an object in the virtual space such that a second position of the object corresponds to the first position. The method further includes determining whether an error occurred in the second position based on the first position failing to be detected correctly. The method further includes moving the object to an erroneous position in the virtual space. The method further includes generating an image including the object at a position immediately before the object has been moved to the erroneous position. The method further includes displaying the image.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 14, 2019
    Inventors: Takeshi KADA, Keisuke NAKAHARA, Koji MIYATA, Yuki KONO
  • Patent number: 9985046
    Abstract: A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: May 29, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Jixin Yu, Koji Miyata, Makoto Yoshida, Johann Alsmeier, Hiro Kinoshita, Daxin Mao
  • Patent number: 9953750
    Abstract: A sintered Nd base magnet segment has a coercive force high at the periphery and lower toward the inside. A method for preparing the magnet includes the steps of: (a) providing a sintered Nd base magnet block having surfaces and a magnetization direction, (b) coating the surfaces of the magnet block excluding the surface perpendicular to the magnetization direction with a Dy or Tb oxide powder, a Dy or Tb fluoride powder, or a Dy or Tb-containing alloy powder, (c) treating the coated block at a high temperature for causing Dy or Tb to diffuse into the block, and (d) cutting the block in a plane perpendicular to the magnetization direction into a magnet segment having a coercive force distribution on the cut section that the coercive force is high at the periphery and lower toward the inside and a constant coercive force distribution in the magnetization direction.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 24, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Koji Miyata, Takehisa Minowa, Hajime Nakamura, Koichi Hirota, Masakatsu Honshima
  • Publication number: 20170358594
    Abstract: A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Zhenyu LU, Jixin YU, Koji MIYATA, Makoto YOSHIDA, Johann ALSMEIER, Hiro KINOSHITA, Daxin MAO
  • Patent number: 9577187
    Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: February 21, 2017
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Akihiro Maesaka, Kazuhiro Ohba, Tetsuya Mizuguchi, Koji Miyata, Motonari Honda, Katsuhisa Aratani
  • Patent number: 9543318
    Abstract: An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Daxin Mao, Koji Miyata, Junichi Ariyoshi, Johann Alsmeier, George Matamis, Wenguang Shi, Jiyin Xu, Xiaolong Hu
  • Patent number: 9502471
    Abstract: A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: November 22, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Henry Chien, Johann Alsmeier, Koji Miyata, Tong Zhang, Man Mui, James Kai, Wenguang Shi, Wei Zhao, Xiaolong Hu, Jiyin Xu, Gerrit Jan Hemink, Christopher Petti
  • Patent number: 9449987
    Abstract: A method of fabricating a memory device is provided. The method includes forming a first alternating stack of insulator layers and spacer material layers over a semiconductor substrate, etching the first alternating stack to expose a single crystalline semiconductor material, forming a first epitaxial semiconductor pedestal on the single crystalline semiconductor material, such that the first epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor material, forming an array of memory stack structures through the first alternating stack, and forming at least one semiconductor device over the first epitaxial semiconductor pedestal.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: September 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Koji Miyata, Zhenyu Lu, Andrew Lin, Daxin Mao, Jixin Yu, Johann Alsmeier, Wenguang Stephen Shi
  • Publication number: 20160104840
    Abstract: A resistive memory includes a memory cell having a first electrode, a second electrode and a resistive memory element between the first electrode and the second electrode. The memory cell includes a thermally insulating region. The thermally insulating region may be included in at least one electrode of the memory cell and/or within an electrically insulating region. The thermally insulating region can confine heat within the memory cell and thereby can reduce the current and/or voltage needed to write information in the resistive memory element.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 14, 2016
    Inventors: Beth Cook, Nirmal Ramaswamy, Shuichiro Yasuda, Scott Sills, Koji Miyata
  • Publication number: 20150333256
    Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Inventors: Akihiro Maesaka, Kazuhiro Ohba, Tetsuya Mizuguchi, Koji Miyata, Motonari Honda, Katsuhisa Aratani
  • Patent number: 9136470
    Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: September 15, 2015
    Assignee: SONY CORPORATION
    Inventors: Akihiro Maesaka, Kazuhiro Ohba, Tetsuya Mizuguchi, Koji Miyata, Motonari Honda, Katsuhisa Aratani
  • Patent number: 9118005
    Abstract: A manufacturing method of a memory apparatus in which memory devices each having a memory layer whose resistance value reversibly varies by voltage application between bottom and upper electrodes are formed, includes: forming and shaping a bottom electrode material film into a first linear pattern extending in a first direction; forming a memory layer material film and an upper electrode material film in this order on the bottom electrode material film; forming the upper electrodes and the memory layers by shaping the upper electrode material film and the memory layer material film into a second linear pattern extending in a second direction intersecting with the first direction; and forming the bottom electrodes having a quadrangle plane shape at regions where the first linear pattern intersect with the second linear pattern by shaping the bottom electrode material film into the second linear pattern.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: August 25, 2015
    Assignee: SONY CORPORATION
    Inventor: Koji Miyata
  • Patent number: 8878307
    Abstract: In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is a doped SiGe shared contact between (a) a gate conductor region shared by an N-channel MOSFET and a P-channel MOSFET and (b) a drain diffusion region of an N-channel MOSFET or of a P-channel MOSFET.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: November 4, 2014
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Koji Miyata
  • Publication number: 20140252471
    Abstract: In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is a doped SiGe shared contact between (a) a gate conductor region shared by an N-channel MOSFET and a P-channel MOSFET and (b) a drain diffusion region of an N-channel MOSFET or of a P-channel MOSFET.
    Type: Application
    Filed: May 14, 2014
    Publication date: September 11, 2014
    Inventor: Koji Miyata
  • Publication number: 20140167895
    Abstract: A sintered Nd base magnet segment has a coercive force high at the periphery and lower toward the inside. A method for preparing the magnet includes the steps of: (a) providing a sintered Nd base magnet block having surfaces and a magnetization direction, (b) coating the surfaces of the magnet block excluding the surface perpendicular to the magnetization direction with a Dy or Tb oxide powder, a Dy or Tb fluoride powder, or a Dy or Tb-containing alloy powder, (c) treating the coated block at a high temperature for causing Dy or Tb to diffuse into the block, and (d) cutting the block in a plane perpendicular to the magnetization direction into a magnet segment having a coercive force distribution on the cut section that the coercive force is high at the periphery and lower toward the inside and a constant coercive force distribution in the magnetization direction.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Koji Miyata, Takehisa Minowa, Hajime Nakamura, Koichi Hirota, Masakatsu Honshima
  • Patent number: 8695210
    Abstract: A method for preparing the magnet includes the steps of: (a) providing a sintered Nd base magnet block having surfaces and a magnetization direction, (b) coating the surfaces of the magnet block excluding the surface perpendicular to the magnetization direction with a Dy or Tb oxide powder, a Dy or Tb fluoride powder, or a Dy or Tb-containing alloy powder, (c) treating the coated block at a high temperature for causing Dy or Tb to diffuse into the block, and (d) cutting the block in a plane perpendicular to the magnetization direction into a magnet segment having a coercive force distribution on the cut section that the coercive force is high at the periphery and lower toward the inside and a constant coercive force distribution in the magnetization direction.
    Type: Grant
    Filed: November 27, 2009
    Date of Patent: April 15, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Koji Miyata, Takehisa Minowa, Hajime Nakamura, Koichi Hirota, Masakatsu Honshima
  • Patent number: 8559210
    Abstract: A memory device includes: a transistor array having transistors; and memory elements provided, one for each of the transistors. The transistor array includes a substrate having diffusion layers on a surface thereof, parallel word lines on the substrate, parallel first bit lines provided in a direction perpendicular to the word lines, bit contact electrodes between the adjacent two word lines and connecting the first bit lines and the diffusion layers, and node contact electrodes at an opposite side to the bit contact electrodes with the two word lines in between and connected to the diffusion layers. The memory elements have lower electrodes connected to the node contact electrodes, memory layers on the lower electrodes and having resistance values reversibly changing by voltage application, and parallel second bit lines extending in the same direction as that of the first bit lines on the memory layers.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: October 15, 2013
    Assignee: Sony Corporation
    Inventors: Koji Miyata, Wataru Otsuka
  • Patent number: D854055
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: July 16, 2019
    Assignee: KCM Corporation
    Inventors: Kazuhiko Hiraoka, Tomoyuki Miyata, Wataru Isaka, Satoshi Kan, Koji Hyodo, Masaki Yoshikawa, Isamu Aoki, Tetsuji Tanaka, Yasunori Miyamoto