Patents by Inventor Koji Soejima

Koji Soejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220098824
    Abstract: A work vehicle includes a vehicle body frame, an engine hood, a first extendable member, and a second extendable member. The vehicle body frame is configured to support an engine. The engine hood has a cover frame coupled to the vehicle body frame so as to allow opening and closing, and an engine cover attached to the cover frame. The first extendable member is coupled to the vehicle body frame and the cover frame. The first extendable member is disposed at one end side relative to a center in a vehicle width direction of the work vehicle. The second extendable member is coupled to the vehicle body frame and the cover frame. The second extendable member is disposed at an other end side relative to the center in the vehicle width direction of the work vehicle.
    Type: Application
    Filed: March 24, 2020
    Publication date: March 31, 2022
    Inventor: Koji SOEJIMA
  • Patent number: 10879227
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 29, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20200118994
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 10580763
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 3, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20190139953
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 10224318
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20180019237
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 18, 2018
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 9863122
    Abstract: A cooling device includes: an introduction pipe configured to introduce a charge air supercharged by a supercharger; a first aftercooler connected to the introduction pipe and configured to cool the charge air; a branch pipe branched from the introduction pipe; a second aftercooler connected to the branch pipe and configured to cool the charge air; and a cooling fan configured to supply a cooling wind to the first aftercooler and the second aftercooler, in which the first aftercooler and the second aftercooler are disposed to be shifted from each other in a rotation axis direction of the cooling fan.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 9, 2018
    Assignee: Komatsu Ltd.
    Inventors: Koji Soejima, Yushi Tanaka, Yuuki Ishikawa
  • Patent number: 9847325
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 19, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20170284058
    Abstract: A cooling device includes: an introduction pipe configured to introduce a charge air supercharged by a supercharger; a first aftercooler connected to the introduction pipe and configured to cool the charge air; a branch pipe branched from the introduction pipe; a second aftercooler connected to the branch pipe and configured to cool the charge air; and a cooling fan configured to supply a cooling wind to the first aftercooler and the second aftercooler, in which the first aftercooler and the second aftercooler are disposed to be shifted from each other in a rotation axis direction of the cooling fan.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Koji Soejima, Yushi Tanaka, Yuuki Ishikawa
  • Publication number: 20170236810
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: November 17, 2016
    Publication date: August 17, 2017
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 9524953
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 20, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20160307875
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 9406602
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: August 2, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20150137348
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 8975750
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20140346681
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 8823174
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: September 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Publication number: 20140103524
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 8685796
    Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: April 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano