Abstract: A semiconductor device-composing substrate 10 has a support base 12, an interconnect layer 14 including interconnects 13, and an insulating resin layer 16. The semiconductor device-composing substrate 10 also has a mounting region D1 on which a semiconductor chip 30 is to be mounted. The insulating resin layer 16 is formed on the interconnect layer 14. Chip-connecting electrodes 17, external electrode pads 18 and the resin stopper patterns 19 are formed in the insulating resin layer 16. The chip-connecting electrodes 17 are provided in the mounting region D1. The external electrode pads 18 are provided outside the mounting region D1. The resin stopper patterns 19 are provided between the mounting region D1 and the external electrode pads 18.

Abstract: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.

Abstract: The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting the solder electrode 22 and connecting it to the electrode pad 16, thus connecting the interconnect substrate 10 and the electronic circuit chip 20. A first metal material, exposed in the surface of the electrode pad 16 opposite to an insulating resin layer 12 and constituting the electrode pad 16, has higher free energy for forming an oxide than a second metal material exposed in the surface of the interconnect 14 opposite to the insulating resin layer 12 and constituting the interconnect 14.

Abstract: The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20 is smaller in area than the opposite end face, i.e. the end face on the side of the IC chip 30. An end face of the via plug 44 on the side of the interconnect layer 10 is smaller in area than the opposite end face, i.e. the end face on the side of the solder balls 60. The thermal decomposition temperature of the insulating resin 14 constituting the interconnect layer 10 is higher than that of the insulating resin 24 constituting the interconnect layer 20.

Abstract: A method of dicing a semiconductor wafer includes providing an interconnect layer providing a protective film on the interconnect layer on the side of a device-forming surface of a silicon wafer, irradiating the protective film with a laser beam to provide a trenched portion that extends through the interconnect layer from the protective film and reaches to an inside of the silicon wafer, removing a portion of the silicon wafer selectively in a depth direction from a bottom of the trenched portion, after irradiating with the laser beam to provide the trenched portion and dividing the silicon wafer along the portion where the trenched portion is provided into respective pieces of the silicon wafer, after removing a portion of the silicon wafer 101 selectively in the depth direction.

Abstract: A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C.

Abstract: A semiconductor device has through electrodes with property as an electrode and excellent in manufacturing stability. The through electrode composed of a conductive small diameter plug and a conductive large diameter plug is provided on the semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area of a connection plug and its diameter each, and the cross sectional area of the small diameter plug is made smaller than a cross sectional area of the large diameter plug and its diameter each. Further, a projecting portion where the small diameter plug is projected from a silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

Abstract: In a semiconductor device, in which an insulating layer is disposed on the main face of the silicon substrate, and the insulating layer includes the protruding portion that protrudes from the end face of the silicon substrate, the protruding portion has an interconnect of Cu embedded within the insulating layer.

Abstract: In a method for fabricating an optical circuit, a mirror element with a protection film formed within a die of a semiconductor is connected to a substrate at a predetermined position. The mirror element with the protection film connected to the substrate is peeled from the die of the semiconductor. The protection film is removed to expose a reflection surface of a reflection film of the mirror element.

Abstract: In a method for fabricating an optical circuit, a mirror element with a protection film formed within a die of a semiconductor is connected to a substrate at a predetermined position. The mirror element with the protection film connected to the substrate is peeled from the die of the semiconductor. The protection film is removed to expose a reflection surface of a reflection film of the mirror element.

Abstract: Disclosed is a bump structure, which has a hollow body, for electrically connecting a first member and a second member. Also disclosed is a method for making a bump structure, which has the steps of: preparing a molding plate with a concave mold to mold a bump-forming member; forming a conductive thin film so as to form a predetermined cavity in the concave mold of the molding plate; preparing a substrate to which the conductive thin film is to be transferred; and transferring the conductive thin film formed on the molding plate to the substrate.

Abstract: A semiconductor manufacturing apparatus for manufacturing a highly versatile semiconductor device includes a holder for releasably embracing and holding a substrate having first and second sides on which first and second bonding pads, respectively, are provided; a bonding tool for wire-bonding the first and second bonding pads; and a bonding head, which has the bonding tool mounted thereon, for driving the bonding tool in three dimensions and rotating the bonding tool about an axis that is perpendicular to the central axis of the bonding tool.

Abstract: Disclosed is a bump structure, which has a hollow body, for electrically connecting a first member and a second member. Also disclosed is a method for making a bump structure, which has the steps of: preparing a molding plate with a concave mold to mold a bump-forming member; forming a conductive thin film so as to form a predetermined cavity in the concave mold of the molding plate; preparing a substrate to which the conductive thin film is to be transferred; and transferring the conductive thin film formed on the molding plate to the substrate.

Abstract: A mounting pin is formed at a pin position on a circuit board or LSI and adopted to set the circuit board or LSI in a mounted state through pin connection. The mounting pin includes a leg standing upright at the pin position, and a locking projection formed at a distal end of the leg to project in one direction and capable of locking with a locking projection of another mounting pin through pin connection. Mounting pins corresponding to each other are set in a pin-connected state by the locking projection when the circuit board and LSI are mounted. A method of manufacturing a mounting pin is also disclosed.

Abstract: In a method for fabricating an optical circuit, a mirror element with a protection film formed within a die of a semiconductor is connected to a substrate at a predetermined position. The mirror element with the protection film connected to the substrate is peeled from the die of the semiconductor. The protection film is removed to expose a reflection surface of a reflection film of the mirror element.

Abstract: One main surface of a substrate has formed on it an appropriate contact terminal having in one part thereof a protruding part. An end of a lead is mounted via a holding part that is provided between the substrate and a probe, the lead being disposed along the main surface of the substrate so as to peel away from the main surface.

Abstract: Disclosed is a bump structure, which has a hollow body, for electrically connecting a first member and a second member. Also disclosed is a method for making a bump structure, which has the steps of: preparing a molding plate with a concave mold to mold a bump-forming member; forming a conductive thin film so as to form a predetermined cavity in the concave mold of the molding plate; preparing a substrate to which the conductive thin film is to be transferred; and transferring the conductive thin film formed on the molding plate to the substrate.

Abstract: A probe card comprises the following elements. An insulation film is provided which is flexible and extends on a first surface of a substrate. The insulation film has a first surface in contact with the first surface of the substrate, to form a space region which is defined between the first surface of the substrate and the first surface of the insulation film so as to allow part of the insulation film to move into the space. Probe patterns extend on a second surface of the insulation film so that the probe patterns.

Abstract: A fabrication method of a plastic-molded lead component is provided, in which leads are aligned at a fine pitch of approximately 100 .mu.m or less with a high accuracy, a simplified process sequence, and a low cost. First, a template having opened V-grooves is prepared. The V-grooves extend along a straight line and are aligned in parallel at a fixed pitch. Second, wire pieces are placed in the respective grooves of the template. Third, the placed pieces of the wire pieces are aligned in parallel on the template at a same pitch as that of the grooves. Fourth, a molding compound is supplied onto the template with or without the use of a mold to bury the aligned wire pieces placed in the grooves. Fifth, the molding compound supplied onto the template is cured to form an encapsulation plastic on the template. The wire pieces placed in the grooves are encapsulated by the encapsulation plastic in such a way that both ends of the wire pieces are exposed from opposite sides of the encapsulation plastic.

Abstract: An IC package includes an IC chip substrate having a first surface on which a plurality of electrodes are formed, and an organic substrate having a first surface on which a plurality of bump electrodes are provided. The organic substrate is combined with the IC chip substrate. Each of the bump electrodes is in contact with a corresponding one of the electrodes on the IC chip substrate. The organic substrate has a plurality of through holes and metallization patterns electrically connecting each of the bump electrodes to a corresponding one of the through holes.