Patents by Inventor Koji Soejima
Koji Soejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110075389Abstract: A semiconductor device comprising a flat wiring board, a first LSI disposed on one surface of the wiring board, a sealing resin for covering the one surface and a side face of the first semiconductor element, and a second LSI disposed on another surface of the wiring board. The wiring board has conductive wiring as a wiring layer, an insulation resin as a support layer for the wiring layer, and a conductive through-hole that passes through the wiring layer and the support layer. Connection points between lands disposed in positions in which the external peripheral edges of the semiconductor elements transverse the interior of the lands as viewed vertically from above, which lands are selected from land portions on which the external connection terminals are formed, and the wiring board formed in the same plane as the lands, are unevenly distributed toward one side of the wiring board.Type: ApplicationFiled: December 3, 2010Publication date: March 31, 2011Applicants: NEC CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Shintaro YAMAMICHI, Katsumi KIKUCHI, Yoichiro KURITA, Koji SOEJIMA
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Patent number: 7892973Abstract: A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.Type: GrantFiled: October 26, 2009Date of Patent: February 22, 2011Assignee: Renesas Electronics CorporationInventors: Masaya Kawano, Koji Soejima, Nobuaki Takahashi
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Patent number: 7889514Abstract: A semiconductor device comprising a flat wiring board, a first LSI disposed on one surface of the wiring board, a sealing resin for covering the one surface and a side face of the first semiconductor element, and a second LSI disposed on another surface of the wiring board. The wiring board has conductive wiring as a wiring layer, an insulation resin as a support layer for the wiring layer, and a conductive through-hole that passes through the wiring layer and the support layer. Connection points between lands disposed in positions in which the external peripheral edges of the semiconductor elements transverse the interior of the lands as viewed vertically from above, which lands are selected from land portions on which the external connection terminals are formed, and the wiring board formed in the same plane as the lands, are unevenly distributed toward one side of the wiring board.Type: GrantFiled: October 10, 2006Date of Patent: February 15, 2011Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Shintaro Yamamichi, Katsumi Kikuchi, Yoichiro Kurita, Koji Soejima
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Patent number: 7880295Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.Type: GrantFiled: November 13, 2009Date of Patent: February 1, 2011Assignees: NEC Corporation, Renesas Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Yoichiro Kurita, Koji Soejima
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Publication number: 20100297811Abstract: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.Type: ApplicationFiled: August 10, 2010Publication date: November 25, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Masaya KAWANO, Koji SOEJIMA, Yoichiro KURITA
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Patent number: 7800233Abstract: A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer 20a on a supporting substrate 70, forming an interconnect layer 10 including an interconnect 18 on the seed metal layer 20a, removing the supporting substrate 70 after forming the interconnect layer 10, and patterning the seed metal layer 20a thus to form an interconnect 20 after removing the supporting substrate.Type: GrantFiled: July 24, 2006Date of Patent: September 21, 2010Assignee: NEC Electronics CorporationInventors: Masaya Kawano, Koji Soejima, Yoichiro Kurita
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Patent number: 7791186Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.Type: GrantFiled: October 4, 2006Date of Patent: September 7, 2010Assignees: NEC Corporation, NEC Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Yoichiro Kurita, Koji Soejima
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Patent number: 7759786Abstract: An insulating layer 12 is formed as a surface layer of electronic circuit chip 10. A conductor interconnect 14 is formed in the insulating layer 12. The conductor interconnect 14 is exposed in the surface of the insulating layer 12. A solder wetting metallic film 16 (a metallic film) is formed on a portion of the conductor interconnect 14 to be exposed in the surface of the insulating layer 12. Typical metallic material (second metallic material) available for composing the solder wetting metallic film 16 includes a material that requires higher free energy for forming an oxide thereof, as compared with a free energy required for forming an oxide of the metallic material composing the conductor interconnect 14.Type: GrantFiled: October 5, 2006Date of Patent: July 20, 2010Assignee: NEC Electronics CorporationInventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano
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Publication number: 20100144091Abstract: A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.Type: ApplicationFiled: February 4, 2010Publication date: June 10, 2010Applicant: NEC Electronics CorporationInventors: Masaya Kawano, Koji Soejima, Nobuaki Takahashi, Yoichiro Kurita, Masahiro Komuro, Satoshi Matsui
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Publication number: 20100127405Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.Type: ApplicationFiled: November 13, 2009Publication date: May 27, 2010Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Katsumi KIKUCHI, Shintaro YAMAMICHI, Yoichiro KURITA, Koji SOEJIMA
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Publication number: 20100087058Abstract: A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.Type: ApplicationFiled: December 10, 2009Publication date: April 8, 2010Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATIONInventors: Koji SOEJIMA, Yoichiro KURITA, Masaya KAWANO, Shintaro YAMAMICHI, Katsumi KIKUCHI
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Publication number: 20100048019Abstract: A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.Type: ApplicationFiled: October 26, 2009Publication date: February 25, 2010Applicant: NEC ELECTRONICS CORPORATIONInventors: Masaya KAWANO, Koji SOEJIMA, Nobuaki TAKAHASHI
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Patent number: 7656046Abstract: A semiconductor device 1 is a semiconductor device of the BGA type, and includes a semiconductor chip 10, a resin layer 20, an insulating layer 30, and an external electrode pad 40. The resin layer 20 is constituted by a sealing resin 22 and an underfill resin 24, and covers the semiconductor chip 10. The insulating layer 30 is formed on the resin layer 20. The external electrode pad 40 is formed in the insulating layer 30. This external electrode pad 40 extends through the insulating layer 30. One surface S1 of the external electrode pad 40 is exposed in the surface of the insulating layer 30, and the other surface S2 is located in the resin layer 20. A concave portion 45 is formed in the surface S2 of the external electrode pad 40. The resin composing the resin layer 20 enters into the concave portion 45.Type: GrantFiled: October 5, 2006Date of Patent: February 2, 2010Assignee: NEC Electronics CorporationInventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano
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Patent number: 7652375Abstract: A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.Type: GrantFiled: April 24, 2007Date of Patent: January 26, 2010Assignees: NEC Electronics Corporation, NEC CorporationInventors: Koji Soejima, Yoichiro Kurita, Masaya Kawano, Shintaro Yamamichi, Katsumi Kikuchi
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Patent number: 7633167Abstract: A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 100 includes: a silicon substrate 101; a through electrode 129 extending through the silicon substrate 101; and a first insulating ring 130 provided in a circumference of a side surface of the through electrode 129 and extending through the semiconductor substrate 101. In addition, the semiconductor device 100 also includes a protruding portion 146, being provided at least in the vicinity of a back surface of a device-forming surface of the semiconductor substrate 101 so as to contact with the through electrode 129, and protruding in a direction along the surface of the semiconductor substrate 101 toward an interior of the through electrode 129.Type: GrantFiled: September 28, 2006Date of Patent: December 15, 2009Assignee: NEC Electronics CorporationInventors: Masaya Kawano, Koji Soejima, Nobuaki Takahashi
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Publication number: 20090273092Abstract: In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.Type: ApplicationFiled: July 17, 2009Publication date: November 5, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano
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Patent number: 7598117Abstract: In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer.Type: GrantFiled: October 16, 2006Date of Patent: October 6, 2009Assignee: NEC Electronics CorporationInventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano
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Patent number: 7538022Abstract: The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting the solder electrode 22 and connecting it to the electrode pad 16, thus connecting the interconnect substrate 10 and the electronic circuit chip 20. A first metal material, exposed in the surface of the electrode pad 16 opposite to an insulating resin layer 12 and constituting the electrode pad 16, has higher free energy for forming an oxide than a second metal material exposed in the surface of the interconnect 14 opposite to the insulating resin layer 12 and constituting the interconnect 14.Type: GrantFiled: September 28, 2006Date of Patent: May 26, 2009Assignee: NEC Electronics CorporationInventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano
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Patent number: 7528068Abstract: A semiconductor device has through electrodes with property as an electrode and excellent in manufacturing stability. The through electrode composed of a conductive small diameter plug and a conductive large diameter plug is provided on the semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area of a connection plug and its diameter each, and the cross sectional area of the small diameter plug is made smaller than a cross sectional area of the large diameter plug and its diameter each. Further, a projecting portion where the small diameter plug is projected from a silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.Type: GrantFiled: March 22, 2005Date of Patent: May 5, 2009Assignee: NEC Electronics CorporationInventors: Koji Soejima, Masaya Kawano
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Patent number: 7495345Abstract: A semiconductor device-composing substrate 10 has a support base 12, an interconnect layer 14 including interconnects 13, and an insulating resin layer 16. The semiconductor device-composing substrate 10 also has a mounting region D1 on which a semiconductor chip 30 is to be mounted. The insulating resin layer 16 is formed on the interconnect layer 14. Chip-connecting electrodes 17, external electrode pads 18 and the resin stopper patterns 19 are formed in the insulating resin layer 16. The chip-connecting electrodes 17 are provided in the mounting region D1. The external electrode pads 18 are provided outside the mounting region D1. The resin stopper patterns 19 are provided between the mounting region D1 and the external electrode pads 18.Type: GrantFiled: October 5, 2006Date of Patent: February 24, 2009Assignee: NEC Electronics CorporationInventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano