Patents by Inventor Kosei Noda

Kosei Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power storage device and method for manufacturing electrode
    Patent number: 9799461
    Abstract: As an electrode for a power storage device, an electrode including a current collector, a first active material layer over the current collector, and a second active material layer that is over the first active material layer and includes a particle containing niobium oxide and a granular active material is used, whereby the charge-discharge cycle characteristics and rate characteristics of the power storage device can be improved. Moreover, contact between the granular active material and the particle containing niobium oxide makes the granular active material physically fixed; accordingly, deterioration due to expansion and contraction of the active material which occur along with charge and discharge of the power storage device, such as powdering of the active material or its separation from the current collector, can be suppressed.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: October 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Kosei Noda, Kazutaka Kuriki, Nobuhiro Inoue
  • Manufacturing method of semiconductor device
    Patent number: 9793383
    Abstract: A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: October 17, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Toshinari Sasaki
  • Display device
    Patent number: 9786689
    Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: October 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
  • SEMICONDUCTOR DEVICE
    Publication number: 20170278976
    Abstract: A semiconductor device including the following components and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a substrate; an oxide semiconductor layer over the substrate; a source electrode and a drain electrode whose end portion has a taper angle and whose upper end portion has a curved surface, the source electrode and the drain electrode being electrically connected to the oxide semiconductor layer; a gate insulating layer being in contact with a part of the oxide semiconductor layer and covering the oxide semiconductor layer, the source electrode, and the drain electrode; and a gate electrode overlapping with the oxide semiconductor layer and being over the gate insulating layer.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Kosei NODA, Yuta ENDO, Toshinari SASAKI
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170271519
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 21, 2017
    Inventors: Toshinari SASAKI, Hitomi SATO, Kosei NODA, Yuta ENDO, Mizuho IKARASHI, Keitaro IMAI, Atsuo ISOBE, Yutaka OKAZAKI
  • Semiconductor device and manufacturing method thereof
    Patent number: 9768279
    Abstract: To provide a transistor formed using an oxide semiconductor film with reduced oxygen vacancies. To provide a semiconductor device that operates at high speed. To provide a highly reliable semiconductor device. To provide a miniaturized semiconductor device. The semiconductor device includes an oxide semiconductor film; a gate electrode overlapping with the oxide semiconductor film; a gate insulating film between the oxide semiconductor film and the gate electrode; and a protective insulating film that is above the oxide semiconductor film, the gate electrode, and the gate insulating film and includes a region containing phosphorus or boron.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Yuichi Sato, Yuta Endo
  • SEMICONDUCTOR DEVICE
    Publication number: 20170263777
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
    Type: Application
    Filed: May 31, 2017
    Publication date: September 14, 2017
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE, Kei TAKAHASHI, Kouhei TOYOTAKA, Masashi TSUBUKU, Kosei NODA, Hideaki KUWABARA
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20170256547
    Abstract: A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair of electrodes separated so that the groove portion is sandwiched therebetween; an oxide semiconductor film which is in contact with the pair of electrodes and side surfaces and a bottom surface of the groove portion and has a thickness value smaller than a depth value of the groove portion; a gate insulating film covering the oxide semiconductor film; and a gate electrode provided to overlap with the oxide semiconductor film with the gate insulating film positioned therebetween.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Inventors: Kosei NODA, Yuta ENDO
  • Semiconductor device and method for manufacturing the same
    Patent number: 9755083
    Abstract: Electrical characteristics of a semiconductor device including the oxide semiconductor are improved. Furthermore, a highly reliable transistor with small variation in electrical characteristics is manufactured. An oxynitride insulating film functioning as a base insulating film and a transistor in contact with the oxynitride insulating film are provided. The transistor includes an oxide semiconductor film in contact with the oxynitride insulating film functioning as a base insulating film. The total amount of gas having a mass-to-charge ratio of 30 released from the oxynitride insulating film by heat treatment and double of the amount of a gas having a mass-to-charge ratio of 32 released from the oxynitride insulating film by heat treatment is greater than or equal to 5×1015/cm2 and less than or equal to 5×1016/cm2, or greater than or equal to 5×1015/cm2 and less than or equal to 3×1016/cm2.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: September 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Satoshi Toriumi, Kazuki Tanemura
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20170236942
    Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Yuta ENDO, Toshinari SASAKI, Kosei NODA
  • Semiconductor device, method for manufacturing semiconductor device, and method for forming oxide film
    Patent number: 9735280
    Abstract: One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3. The spin density is calculated from a peak of a signal detected at a g value (g) of around 1.93 by electron spin resonance spectroscopy. The oxide semiconductor film is formed by a sputtering method while bias power is supplied to the substrate side and self-bias voltage is controlled, and then subjected to heat treatment.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: August 15, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kosei Noda, Suzunosuke Hiraishi
  • Semiconductor device
    Patent number: 9735285
    Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: August 15, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kosei Noda, Kouhei Toyotaka, Kazunori Watanabe, Hikaru Harada
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20170229585
    Abstract: A metal element of a metal film is introduced into the oxide semiconductor film by performing heat treatment in the state where the oxide semiconductor film is in contact with the metal film, so that a low-resistance region having resistance lower than that of a channel formation region is formed. A region of the metal film, which is in contact with the oxide semiconductor film, becomes a metal oxide insulating film by the heat treatment. After that, an unnecessary metal film is removed. Thus, the metal oxide insulating film can be formed over the low-resistance region.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Inventors: Shunpei YAMAZAKI, Yukie SUZUKI, Kosei NODA, Yoshiaki OIKAWA
  • Semiconductor Device and Method for Manufacturing Thereof
    Publication number: 20170221707
    Abstract: A transistor that is formed using an oxide semiconductor film is provided. A transistor that is formed using an oxide semiconductor film with reduced oxygen vacancies is provided. A transistor having excellent electrical characteristics is provided. A semiconductor device includes a first insulating film, a first oxide semiconductor film, a gate insulating film, and a gate electrode. The first insulating film includes a first region and a second region. The first region is a region that transmits less oxygen than the second region does. The first oxide semiconductor film is provided at least over the second region.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Kosei NODA, Yuichi SATO
  • Semiconductor device having a stacked metal oxide
    Patent number: 9722092
    Abstract: To provide a transistor with favorable electrical characteristics. A semiconductor device includes a first insulator over a substrate; a first metal oxide over the first insulator; a second metal oxide over the first metal oxide; a first conductor and a second conductor over the second metal oxide; a third metal oxide over the second metal oxide, the first conductor, and the second conductor; a second insulator over the third metal oxide; and a third conductor over the second insulator. The second metal oxide includes a region in contact with a top surface of the first metal oxide and regions in contact with side surfaces of the first metal oxide. The second metal oxide includes channel formation regions.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Analog circuit and semiconductor device
    Patent number: 9716109
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 25, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE
    Publication number: 20170200748
    Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masashi TSUBUKU, Kosei NODA
  • Semiconductor memory device including memory cell which includes transistor and capacitor
    Patent number: 9691772
    Abstract: A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair of electrodes separated so that the groove portion is sandwiched therebetween; an oxide semiconductor film which is in contact with the pair of electrodes and side surfaces and a bottom surface of the groove portion and has a thickness value smaller than a depth value of the groove portion; a gate insulating film covering the oxide semiconductor film; and a gate electrode provided to overlap with the oxide semiconductor film with the gate insulating film positioned therebetween.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: June 27, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kosei Noda, Yuta Endo
  • Semiconductor device
    Patent number: 9673337
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 6, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
  • Semiconductor device and method for manufacturing the same
    Patent number: 9673305
    Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: June 6, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda