Patents by Inventor Kouichi Nagai
Kouichi Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070097726Abstract: An interlayer insulating film (14) covering a ferroelectric capacitor is formed and a contact hole (19) reaching a top electrode (11a) is formed in the interlayer insulating film (14). An Al wiring (17) connected to the top electrode (11a) via the contact hole (19) is formed on the interlayer insulating film (14). A planer shape of the contact hole (19) is an ellipse.Type: ApplicationFiled: November 20, 2006Publication date: May 3, 2007Applicant: FUJITSU LIMITEDInventor: Kouichi Nagai
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Publication number: 20070080382Abstract: A silicide film is formed between a ferroelectric capacitor structure, which is formed by sandwiching a ferroelectric film between a lower electrode and an upper electrode, and a conductive plug (the conductive material constituting the plug is tungsten (W) for example). Here, an example is shown in which a base film of the conductive plug is the silicide film.Type: ApplicationFiled: April 12, 2006Publication date: April 12, 2007Applicant: FUJITSU LIMITEDInventors: Hideaki Kikuchi, Kouichi Nagai
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Patent number: 7186488Abstract: In a semiconductor device manufacturing method, the step of calculating an exposure time of a photoresist includes (a) a step of deciding whether or not a variation of a line width of a device pattern 104 or a resist pattern 102a in a reference chip in a plurality of semiconductor wafers 101 that are manufactured in the past and have the same wafer information as an subject semiconductor wafer 101 is contained within a tolerance over a plurality of semiconductor wafers 101 in the past, and (b) a step of correcting the exposure time every chip by using an exposure correction table 22 if it is decided in the step (a) that the variation falls within the tolerance.Type: GrantFiled: March 3, 2005Date of Patent: March 6, 2007Assignee: Fujitsu LimitedInventor: Kouichi Nagai
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Publication number: 20070020803Abstract: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.Type: ApplicationFiled: February 28, 2006Publication date: January 25, 2007Applicant: FUJITSU LIMITEDInventors: Kaoru Saigoh, Kouichi Nagai
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Publication number: 20070012976Abstract: A seal ring (102) is formed in a manner to surround each ferroelectric capacitor (101). Additionally, a seal ring (103) is formed in a manner to surround a plurality of ferroelectric capacitors (101). Further, a seal ring (104) is formed in a manner to surround all of the ferroelectric capacitors (101) and along a dicing line (110) inside the dicing line (110).Type: ApplicationFiled: September 18, 2006Publication date: January 18, 2007Applicant: FUJITSU LIMITEDInventors: Tetsuo Yaegashi, Kouichi Nagai
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Publication number: 20070007567Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitoriType: ApplicationFiled: September 12, 2006Publication date: January 11, 2007Applicant: FUJITSU LIMITEDInventors: Tetsuo Yaegashi, Kouichi Nagai
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Publication number: 20060220081Abstract: After a ferroelectric capacitor is formed, an Al wiring (conductive pad) connected to the ferroelectric capacitor is formed. Then, a silicon oxide film and a silicon nitride film are formed around the Al wiring. Thereafter, as a penetration inhibiting film which inhibits penetration of moisture into the silicon oxide film, an Al2O3 film is formed.Type: ApplicationFiled: July 27, 2005Publication date: October 5, 2006Applicant: FUJITSU LIMITEDInventors: Kouichi Nagai, Hitoshi Saito, Kaoru Sugawara, Makoto Takahashi, Masahito Kudo, Kazuhiro Asai, Yukimasa Miyazaki, Katsuhiro Sato, Kaoru Saigoh
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Publication number: 20060223198Abstract: An Al2O3 film with a thickness greater than that of a wiring is formed as a protective film, and then the Al2O3 film is polished by CMP until a conductive barrier film is exposed. Namely, CMP is applied to the Al2O3 film by utilizing the conductive barrier film as a stopper film. Next, a silicon oxide film is formed over the entire surface by, for example, a high-density plasma method, and then the surface thereof is flattened. Subsequently, another Al2O3 film is formed on the silicon oxide film as a protective film for preventing intrusion of hydrogen or moisture. Further, another silicon oxide film is formed on the Al2O3 film, for example, by a high-density plasma method. Then, a via hole reaching the conductive barrier film is formed through the silicon oxide film, the Al2O3 film and the silicon oxide film, and then a W plug is embedded therein.Type: ApplicationFiled: July 29, 2005Publication date: October 5, 2006Applicant: FUJITSU LIMITEDInventors: Hideaki Kikuchi, Kouichi Nagai
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Patent number: 7049169Abstract: According to the present invention, by applying a basic surface-processing agent to a film underlying a resist, the excessive photoacid present at the interface between the resist and the front-end film is neutralized and the pattern shape can be controlled. The present invention provides a method of manufacturing a semiconductor device including the steps of, forming an insulating film on a surface, applying a surface processing agent containing of at least a solvent and a basic component on the insulating film, applying a resist on the insulating film thus applied with the surface processing agent, patterning the resist by lithography, and transferring a resist pattern to the insulating film by a dry etching process.Type: GrantFiled: January 27, 2003Date of Patent: May 23, 2006Assignee: Fujitsu LimitedInventors: Kouichi Nagai, Hideyuki Kanemitsu
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Publication number: 20050285173Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected toType: ApplicationFiled: January 27, 2005Publication date: December 29, 2005Applicant: FUJITSU LIMITEDInventors: Kouichi Nagai, Hideaki Kikuchi, Naoya Sashida, Yasutaka Ozaki
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Publication number: 20050212020Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.Type: ApplicationFiled: May 20, 2005Publication date: September 29, 2005Applicant: FUJITSU LIMITEDInventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
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Publication number: 20050196706Abstract: In a semiconductor device manufacturing method, the step of calculating an exposure time of a photoresist includes (a) a step of deciding whether or not a variation of a line width of a device pattern 104 or a resist pattern 102a in a reference chip in a plurality of semiconductor wafers 101 that are manufactured in the past and have the same wafer information as an subject semiconductor wafer 101 is contained within a tolerance over a plurality of semiconductor wafers 101 in the past, and (b) a step of correcting the exposure time every chip by using an exposure correction table 22 if it is decided in the step (a) that the variation falls within the tolerance.Type: ApplicationFiled: March 3, 2005Publication date: September 8, 2005Applicant: FUJITSU LIMITEDInventor: Kouichi Nagai
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Publication number: 20050127395Abstract: A semiconductor device includes a semiconductor substrate, a circuit part formed on and above the semiconductor substrate, a passivation film covering the circuit part, an electrode pad provided outside the circuit part in such a manner that the electrode pad is exposed from the passivation film, and a guard ring pattern provided between the electrode pad and the circuit part such that the guard ring pattern surrounds the circuit part substantially. The guard ring pattern extends from a surface of the semiconductor substrate to the passivation film.Type: ApplicationFiled: April 30, 2004Publication date: June 16, 2005Applicant: FUJITSU LIMITEDInventors: Kaoru Saigoh, Kouichi Nagai
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Patent number: 6815677Abstract: The present invention provides a scanning electron microscope that can obtain a high-precision SEM image and width measurement values, without damaging an object to be measured even at a high magnification. This scanning electron microscope irradiates a sample with an electron beam so as to detect secondary electrons released from the sample due to the irradiation. The scanning electron microscope also includes scan generators for detecting the secondary electrons at a frequency depending on a detection magnification for the sample. The present invention also provides a method of measuring a pattern size using the above scanning electron microscope.Type: GrantFiled: March 23, 2001Date of Patent: November 9, 2004Assignees: Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Kouichi Nagai, Takahiro Ikeda
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Publication number: 20040048412Abstract: According to the present invention, by applying a basic surface-processing agent to a film underlying a resist, the excessive photoacid present at the interface between the resist and the front-end film is neutralized and the pattern shape can be controlled. The present invention provides a method of manufacturing a semiconductor device including the steps of, forming an insulating film on a surface, applying a surface processing agent containing of at least a solvent and a basic component on the insulating film, applying a resist on the insulating film thus applied with the surface processing agent, patterning the resist by lithography, and transferring a resist pattern to the insulating film by a dry etching process.Type: ApplicationFiled: January 27, 2003Publication date: March 11, 2004Applicant: Fujitsu LimitedInventors: Kouichi Nagai, Hideyuki Kanemitsu
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Publication number: 20040038531Abstract: A method of manufacturing a semiconductor device, including the steps of forming one or more insulation films over a substrate, said one or more insulation films including an insulation film at a top thereof, coating the insulation film with a substrate processing agent, providing resist onto the insulation film coated with the substrate processing agent, lithographically forming a pattern of the resist, and dry-etching the insulation film by using the resist as a mask, wherein the substrate processing agent contains at least a solvent and an acid generating agent.Type: ApplicationFiled: February 10, 2003Publication date: February 26, 2004Applicant: FUJITSU LIMITEDInventors: Kouichi Nagai, Hideyuki Kanemitsu
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Patent number: 6653634Abstract: A method of measuring length with a scanning type electron microscope (SEM) includes the steps of: performing length measurement with the SEM of an already know pattern provided in advance in a predetermined region on a specimen (S 101˜S 104); obtaining a magnification correction coefficient through comparison of the length measurement result with the designed value of the already known pattern (S 105, S 108); and determining a true size by multiplying a measured length value of a measurement point performed by the SEM by the obtained magnification correction coefficient (S 109˜S 111), thereby, a method which is free from a length measurement error regardless to the constitution of the specimen and the film type thereof.Type: GrantFiled: May 22, 2000Date of Patent: November 25, 2003Assignees: Hitachi, Ltd., Fujitsu LimitedInventors: Tadashi Otaka, Kouichi Nagai
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Publication number: 20010035495Abstract: The present invention provides a scanning electron microscope that can obtain a high-precision SEM image and width measurement values, without damaging an object to be measured even at a high magnification. This scanning electron microscope irradiates a sample with an electron beam so as to detect secondary electrons released from the sample due to the irradiation. The scanning electron microscope also includes scan generators for detecting the secondary electrons at a frequency depending on a detection magnification for the sample. The present invention also provides a method of measuring a pattern size using the above scanning electron microscope.Type: ApplicationFiled: March 23, 2001Publication date: November 1, 2001Inventors: Kouichi Nagai, Takahiro Ikeda
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Patent number: 6075776Abstract: A VLAN control system is provided, which comprises: a remote access server, connected to a home network in the VLAN having a global network, for controlling communication between any moved terminal and the home network with reference to a management table for indicating a location of each terminal under connection; a remote access client, connected to each remote network, for controlling communication between the remote network and the global network with reference to a management table for indicating a correspondence relationship between each terminal which is connected to the remote network and the home network; and a VLAN management server, connected to the global network, for managing packet transmission and the location of each terminal with reference to a management table for indicating a correspondence relationship between each terminal and the remote access server and for indicating a location of each terminal under connection.Type: GrantFiled: June 6, 1997Date of Patent: June 13, 2000Assignee: Nippon Telegraph and Telephone CorporationInventors: Shigeaki Tanimoto, Hikoyuki Nakajima, Kunihiko Isoda, Kouichi Nagai, Takashi Masui
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Patent number: 5043190Abstract: Cast-coated papers having high surface gloss, smoothness and high surface strength are produced by applying an aqueous pigment coating onto the surface of a base paper, drying the applied pigment coating to form a cast-coated layer, rewetting the pigment coating layer with a rewetting solution, pressing the rewetted pigment coating layer into contact with a heated, highly polished drum to impart a high gloss surface, the rewetting solution containing a dispersant and/or a release agent as its main components and having its pH adjusted to be between 2 and 4 by incorporation of at least one carboxylic acid selected from the group consisting of formic acid, acetic acid, tartatic acid, citric acid, lactic acid, succinic acid, malic acid and benzoic acid.Type: GrantFiled: April 24, 1990Date of Patent: August 27, 1991Assignee: Nippon Kakoh Saishi K.K.Inventors: Hitoshi Katsumata, Tetsuya Matsumoto, Hirosi Aizawa, Taiji Nakajima, Kouichi Nagai