Patents by Inventor Kouichi Nagai

Kouichi Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090273963
    Abstract: A ferroelectric capacitor comprising a transistor layer superimposed on a semiconductor substrate, a ferroelectric capacitor layer provided superior to the transistor layer, a wiring layer provided superior to the ferroelectric capacitor layer, and a passivation film. Further, at least one layer of barrier film capable of inhibiting penetration of moisture and hydrogen into the underlayer is provided between the ferroelectric capacitor layer and the passivation film, and the passivation film is characterized by containing a novolac resin.
    Type: Application
    Filed: July 15, 2009
    Publication date: November 5, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Kouichi Nagai
  • Publication number: 20090276746
    Abstract: To perform a timing analysis at a high analysis accuracy while reducing a TAT. A circuit analyzer according to the present invention performs a timing analysis on a design target circuit after a layout change. The circuit analyzer includes a storage device in which an extraction range reference is set, an extraction range setting unit and a timing analysis unit. The extraction setting unit sets the extraction range reference including a layout-changed portion, as a parasitic element extraction target range. The timing analysis unit performs a timing analysis by using, as an analysis target, a predetermined range including a parasitic element extracted from the extraction target range.
    Type: Application
    Filed: April 27, 2009
    Publication date: November 5, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Kouichi Nagai
  • Patent number: 7598557
    Abstract: The semiconductor device comprises a first insulation film 26 formed over a semiconductor substrate 10, first conductor plug 32 buried in a first contact hole 28a formed down to a source/drain diffused layer 22, a capacitor 44 formed over the first insulation film 26, a first hydrogen diffusion preventing film 48 formed over the first insulation film 26, covering the capacitor 44, a second insulation film 50 formed over the first hydrogen diffusion preventing film and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the first hydrogen diffusion preventing film 26 and having the surface planarized, a second hydrogen diffusion preventing film 52 formed over the second insulation film 50, second conductor plug 62 buried in a second contact hole 56 formed down to the lower electrode 38 or the upper electrode 42 of the capacitor 44, a third conductor plug 62 buried in a third contact hole 58 formed down to the first conductor plug 32, and an interconnection 64 connected to
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: October 6, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kouichi Nagai, Hideaki Kikuchi, Naoya Sashida, Yasutaka Ozaki
  • Patent number: 7598522
    Abstract: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitori
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: October 6, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tetsuo Yaegashi, Kouichi Nagai
  • Publication number: 20090243038
    Abstract: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.
    Type: Application
    Filed: March 12, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kouichi NAGAI, Kaoru Saigoh
  • Patent number: 7592656
    Abstract: An Al2O3 film with a thickness greater than that of a wiring is formed as a protective film, and then the Al2O3 film is polished by CMP until a conductive barrier film is exposed. Namely, CMP is applied to the Al2O3 film by utilizing the conductive barrier film as a stopper film. Next, a silicon oxide film is formed over the entire surface by, for example, a high-density plasma method, and then the surface thereof is flattened. Subsequently, another Al2O3 film is formed on the silicon oxide film as a protective film for preventing intrusion of hydrogen or moisture. Further, another silicon oxide film is formed on the Al2O3 film, for example, by a high-density plasma method. Then, a via hole reaching the conductive barrier film is formed through the silicon oxide film, the Al2O3 film and the silicon oxide film, and then a W plug is embedded therein.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: September 22, 2009
    Assignee: Fujitsu Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai
  • Patent number: 7592660
    Abstract: There is provided a semiconductor device which includes a base insulating film formed on a semiconductor substrate, a capacitor formed on the base insulating film, an interlayer insulating film covering the capacitor, a first layer metal wiring formed on the interlayer insulating film, a single-layer first insulating film which covers the interlayer insulating film and the first layer metal wiring and has a first film thickness above the first layer metal wiring, a first capacitor protective insulating film formed on the first insulating film, a first cover insulating film which is formed on the first capacitor protective insulating film and has a second film thickness thicker than the first film thickness, above the first layer metal wiring, a third hole formed in the insulating films on the first layer metal wiring, and a fifth conductive plug formed in the third hole.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: September 22, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kouichi Nagai, Wensheng Wang
  • Publication number: 20090181474
    Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 16, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Kouichi NAGAI
  • Publication number: 20090160023
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Application
    Filed: February 24, 2009
    Publication date: June 25, 2009
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • Publication number: 20090117671
    Abstract: A method for manufacturing a semiconductor device includes the step of conducting an acceptance/rejection judgment about the semiconductor device. The acceptance/rejection judgment is conducted by using a hysteresis loop that indicates the relationship between the applied voltage and the polarization quantity of the ferroelectric capacitor.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 7, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Kouichi NAGAI
  • Patent number: 7504341
    Abstract: A method of manufacturing a semiconductor device, including the steps of forming one or more insulation films over a substrate, said one or more insulation films including an insulation film at a top thereof, coating the insulation film with a substrate processing agent, providing resist onto the insulation film coated with the substrate processing agent, lithographically forming a pattern of the resist, and dry-etching the insulation film by using the resist as a mask, wherein the substrate processing agent contains at least a solvent and an acid generating agent.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: March 17, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kouichi Nagai, Hideyuki Kanemitsu
  • Publication number: 20090024274
    Abstract: There is provided a recording device capable of collecting information which makes it possible to investigate an accident. A recording section, such as a FeRAM, records vehicle information indicative of current conditions of the vehicle at predetermined recording intervals. An accident level-determining section determines whether or not an accident has occurred, based on a magnitude of an impact on the vehicle detected by an impact-detecting section. When it is determined that an accident has occurred, a recording control section causes the recording section to record the vehicle information at the recording intervals (e.g. 0.1 seconds) shorter than those (e.g. 1 second) before the accident. This makes it possible to use pre-accident information and post-accident information to thereby investigate an accident in more detail.
    Type: Application
    Filed: September 25, 2008
    Publication date: January 22, 2009
    Applicant: FUJITSU MICROELECTONICS LIMITED
    Inventor: Kouichi NAGAI
  • Publication number: 20090008783
    Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 8, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kaoru SAIGOH, Kouichi NAGAI
  • Publication number: 20080258260
    Abstract: A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over the insulation film and including an alloy film of aluminum and magnesium.
    Type: Application
    Filed: May 28, 2008
    Publication date: October 23, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Kouichi NAGAI, Kaoru Saigoh
  • Publication number: 20080258195
    Abstract: A ferroelectric capacitor is formed above a semiconductor substrate (1), and thereafter, wirings (24a) are formed. A barrier film (25) covering the wirings (24a) is formed. A silicon oxide film (26) embedding gaps between the adjacent wirings (24a) is formed. The silicon oxide film (26) is polished until a surface of the barrier film (25) is exposed by a CMP method. A barrier film (27) is formed on the barrier film (25) and the silicon oxide film (26). Aluminum oxide films are formed as the barrier films (25, 27).
    Type: Application
    Filed: June 27, 2008
    Publication date: October 23, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hiroki SUGAWARA, Kouichi NAGAI
  • Publication number: 20080258262
    Abstract: A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above the semiconductor substrate and connected to the multilevel wiring structure. The pad electrode structure includes pad wiring patterns and pad via conductors interconnecting the pad wiring patterns, the uppermost pad wiring pattern includes a pad pattern and a sealing pattern surrounding the pad pattern in a loop shape. Another pad wiring pattern has continuous extended pad pattern of a size overlapping the sealing pattern. The pad via conductors include a plurality of columnar via conductors disposed in register with the pad pattern and a loop-shaped wall portion disposed in register with the sealing pattern.
    Type: Application
    Filed: June 27, 2008
    Publication date: October 23, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Kouichi Nagai
  • Publication number: 20080237795
    Abstract: There is provided a semiconductor device which includes a base insulating film formed on a semiconductor substrate, a capacitor formed on the base insulating film, an interlayer insulating film covering the capacitor, a first layer metal wiring formed on the interlayer insulating film, a single-layer first insulating film which covers the interlayer insulating film and the first layer metal wiring and has a first film thickness above the first layer metal wiring, a first capacitor protective insulating film formed on the first insulating film, a first cover insulating film which is formed on the first capacitor protective insulating film and has a second film thickness thicker than the first film thickness, above the first layer metal wiring, a third hole formed in the insulating films on the first layer metal wiring, and a fifth conductive plug formed in the third hole.
    Type: Application
    Filed: June 2, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Kouichi NAGAI, Wensheng WANG
  • Publication number: 20080217668
    Abstract: After a ferroelectric capacitor (1) is formed and before a wiring (15) to be a pad is formed, an alumina film (11) is formed as a diffusion suppressing film suppressing diffusion of hydrogen and moisture. Subsequently, the wiring (15) is formed and an SOG film (16) is formed thereon. Then, a silicon nitride film (17) is formed on the SOG film (16).
    Type: Application
    Filed: October 11, 2006
    Publication date: September 11, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Kouichi Nagai
  • Publication number: 20080203576
    Abstract: A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 28, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hideaki KIKUCHI, Kouichi NAGAI, Tomoyuki KIKUCHI
  • Publication number: 20080197506
    Abstract: A semiconductor device manufacturing method, includes the steps of forming an insulating film over a semiconductor substrate, thinning selectively a thick portion, whose film thickness is thicker than a reference value, of the insulating film, forming contact holes in a thinned portion of the insulating film 25, and forming conductive plugs in the contact holes.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 21, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Kouichi NAGAI