Abstract: An output circuit includes an analog amplifier circuit including a differential amplifier stage configured to receive an input voltage, and first to nth output systems (n is a natural number more than 1); first to nth output nodes; an output pad; and first to nth electrostatic protection resistances. An ith output system (i is a natural number between 2 and n) of the first to nth output systems includes an ith PMOS transistor having a drain connected with the ith output node of the first to nth output nodes and a gate connected with a first output of the differential amplifier stage; and an ith NMOS transistor having a drain connected with the ith output node and a gate connected with a second output of the differential amplifier stage. The first to nth electrostatic protection resistances are respectively connected between the first to nth output nodes and the output pad.

Abstract: A display panel driver is provided with: first and second amplifiers; first to n-th even output nodes, n being an integer of two or more; first to n-th odd output nodes; first and second output pads connected to data lines of a display panel, respectively; first to n-th switch blocks; first to n-th even electrostatic protection resistors; and first to n-th odd electrostatic protection resistors. The i-th switch block out of the first to n-th switch blocks is configured to switch connections between the first and second amplifiers and i-th even and odd electrostatic protection resistors out of the first to n-th even and odd electrostatic protection resistors. The first to n-th even electrostatic protection resistors are connected between the first to n-th even output nodes and the first output pad, respectively. The first to n-th odd electrostatic protection resistors are connected between the first to n-th odd output nodes and the second output pad, respectively.

Abstract: An operational amplifier includes an input differential stage having one external input receiving an external input voltage and two outputs; and two output stages. A switch section is provided between inputs of the two output stages and the two outputs of the input differential stage, and is configured to alternately connect the two outputs of the input differential stage and inputs of a positive-only output stage of the two output stages; and the two outputs of the input differential stage and inputs of a negative-only output stage of the two output stages.

Abstract: An operational amplifier includes an input stage amplifier that receives an input signal, an output stage amplifier that amplifies a signal output from the input stage amplifier and outputs the signal, a capacitor that is connected between an input node and an output node of the output stage amplifier, and a charge and discharge control circuit that controls a charge and discharge current of the capacitor.

Abstract: Disclosed is a differential amplifier which comprises a differential pair comprising depletion-type first and second N-channel MOS transistors, a first current source that supplies a current for the differential pair, a current mirror circuit formed by transistor pairs connected in cascode fashion in two stages, for connecting an output pair of the differential pair in folded connection, second and third current sources connected to an input terminal of the current mirror circuit and an output terminal of the current circuit, respectively, and a buffer amplifier with that has an input terminal connected to the output terminal of the current mirror circuit and has an output terminal connected to an output terminal of the differential amplifier.

Abstract: An operational amplifier circuit includes: an input stage for generating an internal current corresponding to a potential difference between inverting and non-inverting input terminals; and an output stage for driving an output terminal in response to the internal current. The output terminal includes: a floating current source through which the internal current flows; a PMOS transistor for driving the output terminal corresponding to a potential of a first terminal of the floating current source; and an NMOS transistor for driving the output terminal corresponding to a potential of a second terminal of the floating current source. The floating current source includes: a PMOS transistor whose source and drain are respectively connected to the first and second terminals; and an NMOS transistor whose drain and source are respectively connected to the first and second terminals. A depletion transistor is used as the latter NMOS transistor.

Abstract: An operational amplifier includes an input stage amplifier that receives an input signal, an output stage amplifier that amplifies a signal output from the input stage amplifier and outputs the signal, a capacitor that is connected between an input node and an output node of the output stage amplifier, and a charge and discharge control circuit that controls a charge and discharge current of the capacitor.

Abstract: A small-offset operational amplifier circuit with a simple circuit architecture is provided. An operational amplifier circuit includes: differential pair sections (MN1 and MN2, MP1 and MP2); a first switch section (SG3); folded cascode-connected current mirror circuit sections (MP3 to MP6, MN3 to MN6); a second switch section (SG1 and SG2); and a buffer amplifier (BA), wherein the operational amplifier circuit interlockingly switches between the first switch section (SG3) and the second switch section (SG1 and SG2) so as to spatially disperse offset voltage and equivalently cancel offset.

Abstract: Provided is a display panel driver with an improved driving characteristic by use of an amplifier output having excellent symmetry of an output characteristic. The display panel driver according to the present invention includes a first input differential stage circuit, a first output stage circuit, a second output stage circuit, and a first switch circuit. The first input differential stage circuit outputs two first input stage output signals according to one of a positive voltage and a negative voltage. The first switch circuit selects one of the first and second output stage circuits, and connects the selected circuit to the first input differential stage circuit. The output stage circuit connected to the first input differential stage circuit outputs a single-ended signal based on the two first input stage output signals from the first input differential stage circuit.

Abstract: An operational amplifier circuit includes: an input stage for generating an internal current corresponding to a potential difference between inverting and non-inverting input terminals; and an output stage for driving an output terminal in response to the internal current. The output terminal includes: a floating current source through which the internal current flows; a PMOS transistor for driving the output terminal corresponding to a potential of a first terminal of the floating current source; and an NMOS transistor for driving the output terminal corresponding to a potential of a second terminal of the floating current source. The floating current source includes: a PMOS transistor whose source and drain are respectively connected to the first and second terminals; and an NMOS transistor whose drain and source are respectively connected to the first and second terminals. A back gate of the latter PMOS transistor is connected to the source thereof.

Abstract: An operational amplifier circuit includes: an input differential stage circuit supplied with power supply voltages in a first voltage range; and an output stage circuit supplied with power supply voltages in a second voltage range which is different from the first voltage range. The operational amplifier circuit amplifies a signal supplied to the input differential stage circuit and outputs the amplified signal from the output stage circuit to drive a load.

Abstract: The present invention enables rising and falling slew rates to be symmetrized and secures a drive current at the time of 2H inversion driving. An operational amplifier in accordance with one aspect of the present invention includes: a first output transistor and a second output transistor connected in series between a first power supply and a second power supply; an output terminal connected to a node between the first output transistor and the second output transistor; a phase-compensating element provided either between the gate of the first output transistor and the output terminal or between the gate of the second output transistor and the output terminal; and a floating current source connected between the gate of the first output transistor and the gate of the second output transistor.

Abstract: To reduce the apparent effect of offset voltage by making the offset voltage spatially scattered.

Abstract: A voltage comparator circuit is composed of a differential amplifier circuit receiving a pair of input signals to develop an output signal on an output terminal, and a waveform shaping circuit connected to the output terminal.

Abstract: A data driver used for driving a display panel is provided with a grayscale voltage generator circuit generating a plurality of grayscale voltages; and a drive circuitry selecting a selected grayscale voltage from the plurality of grayscale voltages in response to input display data, and outputting a data signal having a voltage level corresponding to the selected grayscale voltage to the display panel. The grayscale voltage generator circuit comprises an amplifier generating a voltage bias; and a voltage generator circuit generating the plurality of grayscale voltages from the voltage bias. The amplifier is designed so that a polarity of an offset voltage of the amplifier is reversible.

Abstract: The present invention provides a driving circuit capable of exerting improved driving performance while saving power consumption. A capacitive load driving circuit includes a gate driver, which drives scan electrodes aligned in a column direction of capacitive load circuits arranged in a matrix, and a source driver, which drives data electrodes aligned in a row direction of the capacitive load circuits. The source driver includes a plurality of output circuits, which are aligned in the row direction, for driving the respective data electrodes. Each of the plurality of output circuits drives the corresponding data electrode after changing the pre-charge amount on the basis of the position of the scan electrode driven by the gate driver.

Abstract: A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.

Abstract: An operational amplifier includes a differential pair section; a load section configured to function as active load of the differential pair section; and a switch section configured to switch supply of a differential input signal to the differential pair section and to switch connection of outputs of the differential pair section to the load section. The switch section is operated to cancel an offset voltage of the operation amplifier.

Abstract: A source driver which can control the spatial cycle of inverting the polarity of offset voltage in response to the spatial cycle of inverting the polarity of data signal. The liquid crystal display device according to the present invention has an LCD panel, having data lines, and source drivers for supplying data signal to the data lines. The source driver includes an offset cancel control circuit for generating an offset cancel control signal and an amplifier used for generating the data signal, which is configured so as to invert the polarity of the offset voltage in response to the offset cancel control signal OCC. The offset cancel controller circuit receives the pattern select signal PSEL specifying the cycle of inverting the polarity of the offset voltage of the amplifier to generate the offset cancel control signal in response to the pattern select signal PSEL.

Abstract: A differential amplifier includes an input stage circuit including a first differential pair and a second differential pair which are complementary to each other; a first current mirror circuit connected with the first differential pair and configured to function as an active load; a second current mirror circuit connected with the second differential pair and configured to function as an active load; an output stage circuit having a pair of output transistors connected in series between a higher power supply and a lower power supply; an operation point setting circuit configured to set an operation point of the output transistors; and a floating constant current source connected between an input terminal of the first current mirror circuit and an input terminal of the second current mirror circuit, and configured to supply a constant current.