Abstract: To automatically control a spatial cycle at which a polarity of an offset voltage is inverted corresponding to a spatial cycle at which a polarity of a data signal is inverted, and satisfactorily maintain the quality of the display image, the present invention provides a liquid crystal display apparatus including a liquid crystal display panel (1) having a data line (11) and a source driver (3) for supplying a data signal to the data line (11) based on a polarity signal (POL). A polarity of the data signal is determined based on the polarity signal (POL). The source driver (3) includes an offset cancel control circuit (40) for generating an offset cancel control signal (OCC) and an output amplifier (38) used to generate the data signal. The output amplifier (38) is constructed so as to invert a polarity of an offset voltage based on the offset cancel control signal (OCC). The offset cancel control signal (OCC) is generated based on the polarity signal (POL).

Abstract: A capacitive load driving circuit includes a gate driver, and a source driver. The gate driver drives a plurality of capacitive loads arranged in a matrix form in a row direction. The source driver drives the plurality of capacitive loads in a column direction. The source driver includes a plurality of output circuits configured to be arranged in a row direction. Each of the plurality of output circuits changes a slew rate based on a column position of a capacitive load of the plurality of capacitive loads driven by the gate driver.

Abstract: To reduce the apparent effect of offset voltage by making the offset voltage spatially scattered.

Abstract: A voltage comparator that realizes high-speed operation with a simple structure includes an input differential stage having a first differential pair and a second differential pair, into which a differential voltage is inputted from differential input terminals In+ and In?, with reverse polarity to each other, folded cascode-type differential stages, which adds a differential output signal of the first differential pair and a differential output signal of the second differential pair and is connected to a differential output of the input differential stage, and oppositely disposed first and second current mirror circuits, which receive differential outputs of the folded cascode-type differential stages into their respective inputs, with reverse polarity to each other and their outputs connected in common to an output terminal. The folded cascode-type differential stage adds the differential output signal of the first differential pair and the differential output signal of the second differential pair.

Abstract: It was difficult to design an operational amplifier which can cancel an offset to drive a liquid crystal display. An operational amplifier includes: a first differential pair having a first transistor and a second transistor of a first conduction type; a second differential pair having a third transistor and a fourth transistor of a second conduction type; a first floating current source; a second floating current source; and an output stage having a fifth transistor and a sixth transistor, in which, when an input signal is applied to the first and third transistor, an electric current which flows into the fifth transistor and the sixth transistor is set by the first floating current source, and when the input signal is applied to the second and fourth transistor, an electric current which flows into the fifth transistor and the sixth transistor is set by the second floating current source.

Abstract: A differential amplifier circuit receives a pair of input signals to develop an output signal. First and second MOS transistors have commonly-connected gates and sources. A third MOS transistor has a drain connected to the commonly-connected gates, and a source connected to the first MOS transistor's drain. The third MOS transistor's gate is connected to a constant voltage source. A constant current source is connected to the third MOS transistor's drain. A first terminal, connected to the first MOS transistor's drain and to the third MOS transistor's source, provides an input current. A second terminal, connected to the first and second MOS transistors' commonly-connected sources, provides a common reference. A third terminal, connected to the second MOS transistor's drain, provides an output current.

Abstract: To provide a temperature detection circuit and a semiconductor device capable of accurately detecting temperatures. A temperature detection circuit 10 includes a group of diodes 11 connected in series, a constant current source I1 connected to the group of diodes 11, a BGR circuit 13, an amplifier 14 for amplifying the BGR voltage, an adder 12 for subtracting a comparison voltage VD generated by the group of diodes 11 from a reference voltage serving as an output of the amplifier 14, a voltage current converter 15 for converting the output voltage of the adder 12 into the current, and a resistor R2 for converting its output current into the voltage. The reference voltage VA2 is a BGR voltage VBGR amplified by the same voltage as the comparison voltage VD at a predetermined temperature T1.

Abstract: A driver circuit includes a differential amplifier for receiving an input signal, and first and second transistors of different conductivity types. The first and second transistors are connected serially between two power supply terminals in a form (source follower) in which the sources of the transistors are connected to an output point, for push-pull driving the output point in response to an output signal from the differential amplifier.

Abstract: A liquid crystal display (LCD) driver integrated circuit includes a grayscale voltage generating circuit configured to generate a plurality of grayscale voltages from a set of supply reference voltages; and a converting section having connection terminals and configured to drive each of a plurality of data lines of a liquid crystal display panel through one of the connection terminals based on one of the plurality of grayscale voltages which is determined based on an input data, when each of a plurality of scanning lines of the liquid crystal display panel is driven. The grayscale voltage generating circuit includes a resistance circuit having resistances connected in series; and a plurality of voltage buffers connected to the resistance circuit to bias the resistance circuit.

Abstract: A display driver for evenly display the screen driven by a plurality of driver circuits is provided. The display apparatus includes a display panel driven by data lines and driver units. Each of the data lines is driven by the corresponding driver unit. Each of the driver units has a resistance division unit for generating grayscale voltages, an operational amplifier unit for supplying voltages to the terminals of the resistance division unit in response to a bias control signal. The corresponding terminals of the resistance division unit of the plurality of driver circuits are commonly connected. The bias control signal is supplied when each of the driver circuit drives the corresponding data line.

Abstract: A gray scale voltage generating circuit includes a first resistor ladder circuit, connected between a high voltage power supply terminal and a low voltage power supply terminal and having nodes for outputting respective reference voltages, a second resistor ladder circuit, connected between the high voltage power supply terminal and the low voltage power supply terminal, and plural voltage follower circuits, connected between the respective nodes of the second resistor ladder circuit and the respective nodes of the first resistor ladder circuit with first resistor provided between the n/2'th node voltage and the high voltage power supply terminal and a second resistor provided between the n/2+1'th node voltage and the low voltage power supply terminal.

Abstract: Differential amplifier includes a differential amplifier circuit, a bias circuit and an output circuit. The differential amplifier circuit includes first and second differential amplifier sections. The first differential amplifier section includes a first PMOS transistor which has a source connected with a power supply line, and a first pair of PMOS transistors which have sources connected with a drain of the first PMOS and gates respectively receiving first and second input voltages. The second differential amplifier section includes a first NMOS transistor which has a source connected with a ground line, and a second pair of NMOS transistors which have sources connected with a drain of the first NMOS and gates respectively receiving the first and second input voltages. The bias circuit activates one of the amplifier sections in response to a control signal. The output circuit outputs an output signal from an output of the activated differential amplifier section.

Abstract: Disclosed is a differential amplifier which comprises a differential pair comprising depletion-type first and second N-channel MOS transistors, a first current source that supplies a current for the differential pair, a current mirror circuit formed by transistor pairs connected in cascode fashion in two stages, for connecting an output pair of the differential pair in folded connection, second and third current sources connected to an input terminal of the current mirror circuit and an output terminal of the current circuit, respectively, and a buffer amplifier with that has an input terminal connected to the output terminal of the current mirror circuit and has an output terminal connected to an output terminal of the differential amplifier.

Abstract: A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.

Abstract: A grayscale voltage generating circuit includes a first constant-voltage source for generating a high potential; a second constant-voltage source for generating a low potential; ? resistor connected between outputs of the first and second constant-voltage sources; a difference voltage detecting circuit for detecting a difference voltage across the ? resistor; and a voltage-to-current converting circuit for converting the difference voltage to a current by a resistor and outputting the current as a source current and a sink current. The source current output and sink current output of the voltage-to-current converting circuit are connected to the high and low potential sides, respectively, of the ? resistor.

Abstract: A novel polypeptide, a polynucleotide encoding this polypeptide, an expression vector comprising this polynucleotide, a cell transfected with the expression vector, an antibody binding to the above polypeptide, a convenient screening method for obtaining an agent for treating joint diseases, and a process for manufacturing a pharmaceutical composition for treating joint diseases are disclosed. The polypeptide is a novel aggrecanase causative of joint diseases (particularly an OA disease).

Abstract: A differential amplifier circuit includes a first differential transistor pair, a second differential transistor pair, an adder section and an amplifying unit. The first differential transistor pair receives first and second input signals and an output signal as a third input signal, and the second differential transistor pair receives the first and second input signals and the output signal as a fourth input signal. The adder section adds first output signals from the first differential transistor pair and second output signals from the second differential transistor pair, and the amplifying unit amplifies an addition resultant signal from the adder section to output to the first and second differential transistor pairs.

Abstract: An operational amplifier includes a differential pair section; a load section configured to function as active load of the differential pair section; and a switch section configured to switch supply of a differential input signal to the differential pair section and to switch connection of outputs of the differential pair section to the load section. The switch section is operated to cancel an offset voltage of the operation amplifier.

Abstract: A differential amplifier includes an input stage circuit including a first differential pair and a second differential pair which are complementary to each other; a first current mirror circuit connected with the first differential pair and configured to function as an active load; a second current mirror circuit connected with the second differential pair and configured to function as an active load; an output stage circuit having a pair of output transistors connected in series between a higher power supply and a lower power supply; an operation point setting circuit configured to set an operation point of the output transistors; and a floating constant current source connected between an input terminal of the first current mirror circuit and an input terminal of the second current mirror circuit, and configured to supply a constant current.

Abstract: Disclosed is a gray scale voltage generating circuit which includes a first resistor ladder circuit, connected between a high voltage power supply terminal and a low voltage power supply terminal and having nodes for outputting respective reference voltages, a second resistor ladder circuit, connected between the high voltage power supply terminal and the low voltage power supply terminal, and plural voltage follower circuits, connected between the respective nodes of the second resistor ladder circuit and the respective nodes of the first resistor ladder circuit. There are provided a first resistor between the n/2'th node voltage and the high voltage power supply terminal and a second resistor between the n/2+1'th node voltage and the low voltage power supply terminal.