Patents by Inventor Kouichi Nishimura

Kouichi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060186934
    Abstract: A driver circuit includes a differential amplifier for receiving an input signal, and first and second transistors of different conductivity types. The first and second transistors are connected serially between two power supply terminals in a form (source follower) in which the sources of the transistors are connected to an output point, for push-pull driving the output point in response to an output signal from the differential amplifier.
    Type: Application
    Filed: April 19, 2006
    Publication date: August 24, 2006
    Inventor: Kouichi Nishimura
  • Patent number: 7094590
    Abstract: A novel polypeptide, a polynucleotide encoding this polypeptide, an expression vector comprising this polynucleotide, a cell transfected with the expression vector, an antibody binding to the above polypeptide, a convenient screening method for obtaining an agent for treating joint diseases, and a process for manufacturing a pharmaceutical composition for treating joint diseases are disclosed. The polypeptide is a novel aggrecanase causative of joint diseases (particularly an OA disease).
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: August 22, 2006
    Assignee: Astellas Pharma Inc.
    Inventors: Noboru Yamajii, Kouichi Nishimura, Kunitake Abe
  • Patent number: 7075342
    Abstract: A driver circuit includes a differential amplifier for receiving an input signal, and first and second transistors of different conductivity types. The first and second transistors are connected serially between two power supply terminals in a form (source follower) in which the sources of the transistors are connected to an output point, for push-pull driving the output point in response to an output signal from the differential amplifier.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: July 11, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Kouichi Nishimura
  • Publication number: 20060103433
    Abstract: A voltage comparator circuit is composed of a differential amplifier circuit receiving a pair of input signals to develop an output signal on an output terminal, and a waveform shaping circuit connected to the output terminal.
    Type: Application
    Filed: November 16, 2005
    Publication date: May 18, 2006
    Applicant: NEC Electronics Corporation
    Inventor: Kouichi Nishimura
  • Publication number: 20060078957
    Abstract: A novel polypeptide, a polynucleotide encoding this polypeptide, an expression vector comprising this polynucleotide, a cell transfected with the expression vector, an antibody binding to the above polypeptide, a convenient screening method for obtaining an agent for treating joint diseases, and a process for manufacturing a pharmaceutical composition for treating joint diseases are disclosed. The polypeptide is a novel aggrecanase causative of joint diseases (particularly an OA disease).
    Type: Application
    Filed: November 23, 2005
    Publication date: April 13, 2006
    Inventors: Noboru Yamajii, Kouichi Nishimura, Kunitake Abe
  • Publication number: 20050275459
    Abstract: A voltage comparator that realizes high-speed operation with a simple structure includes an input differential stage having a first differential pair and a second differential pair, into which a differential voltage is inputted from differential input terminals In+ and In?, with reverse polarity to each other, folded cascode-type differential stages, which adds a differential output signal of the first differential pair and a differential output signal of the second differential pair and is connected to a differential output of the input differential stage, and oppositely disposed first and second current mirror circuits, which receive differential outputs of the folded cascode-type differential stages into their respective inputs, with reverse polarity to each other and their outputs connected in common to an output terminal. The folded cascode-type differential stage adds the differential output signal of the first differential pair and the differential output signal of the second differential pair.
    Type: Application
    Filed: June 9, 2005
    Publication date: December 15, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kouichi Nishimura
  • Publication number: 20050093629
    Abstract: A differential amplifier circuit includes a first differential transistor pair, a second differential transistor pair, an adder section and an amplifying unit. The first differential transistor pair receives first and second input signals and an output signal as a third input signal, and the second differential transistor pair receives the first and second input signals and the output signal as a fourth input signal. The adder section adds first output signals from the first differential transistor pair and second output signals from the second differential transistor pair, and the amplifying unit amplifies an addition resultant signal from the adder section to output to the first and second differential transistor pairs.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 5, 2005
    Inventors: Kouichi Nishimura, Atsushi Shimatani
  • Publication number: 20050062508
    Abstract: A driver circuit includes a differential amplifier for receiving an input signal, and first and second transistors of different conductivity types. The first and second transistors are connected serially between two power supply terminals in a form (source follower) in which the sources of the transistors are connected to an output point, for push-pull driving the output point in response to an output signal from the differential amplifier.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 24, 2005
    Inventor: Kouichi Nishimura
  • Publication number: 20040242171
    Abstract: A transmitter circuit for use in a display device of the type having a transmission line consisting of aluminum or copper conductor formed on a glass substrate includes a driver circuit, which has a non-inverting output terminal and an inverting output terminal, for outputting a signal current, which has a loop direction that changes based upon an input signal, to the non-inverting and inverting output terminals; and an output-waveform control circuit for detecting the edge of the waveform of the input signal and responding by increasing the signal current temporarily.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 2, 2004
    Applicant: NEC Electronics Corporation
    Inventors: Akio Hosokawa, Kouichi Nishimura
  • Publication number: 20040189386
    Abstract: Differential amplifier includes a differential amplifier circuit, a bias circuit and an output circuit. The differential amplifier circuit includes first and second differential amplifier sections. The first differential amplifier section includes a first PMOS transistor which has a source connected with a power supply line, and a first pair of PMOS transistors which have sources connected with a drain of the first PMOS and gates respectively receiving first and second input voltages. The second differential amplifier section includes a first NMOS transistor which has a source connected with a ground line, and a second pair of NMOS transistors which have sources connected with a drain of the first NMOS and gates respectively receiving the first and second input voltages. The bias circuit activates one of the amplifier sections in response to a control signal. The output circuit outputs an output signal from an output of the activated differential amplifier section.
    Type: Application
    Filed: March 16, 2004
    Publication date: September 30, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kouichi Nishimura
  • Publication number: 20040142445
    Abstract: This invention provides a novel metalloprotease having an aggrecanase activity which causes joint diseases, a gene coding for this metalloprotease, a promoter of the above metalloprotease, a method for screening a drug with the use of the above metalloprotease and a pharmaceutical composition for inhibiting degradation of proteoglycans, which comprises as the active ingredient a substance capable of inhibiting the aggrecanase activity of the above metalloprotease.
    Type: Application
    Filed: January 26, 2004
    Publication date: July 22, 2004
    Applicants: YAMANOUCHI PHARMACEUTICAL CO., LTD., KAZUSA DNA RESEARCH INSTITUTE
    Inventors: Noboru Yamaji, Kouichi Nishimura, Kunitake Abe, Osamu Ohara, Takahiro Nagase, Nobuo Nomura
  • Patent number: 6716613
    Abstract: This invention provides a novel metalloprotease having an aggrecanase activity which causes joint diseases, a gene coding for this metalloprotease, a promoter of the above metalloprotease, a method for screening a drug with the use of the above metalloprotease and a pharmaceutical composition for inhibiting degradation of proteoglycans, which comprises as the active ingredient a substance capable of inhibiting the aggrecanase activity of the above metalloprotease.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: April 6, 2004
    Assignees: Yamanouchi Pharmaceutical Co., Ltd., Kazusa DNA Research Institute
    Inventors: Noboru Yamaji, Kouichi Nishimura, Kunitake Abe, Osamu Ohara, Takahiro Nagase, Nobuo Nomura
  • Publication number: 20030185828
    Abstract: A novel polypeptide, a polynucleotide encoding this polypeptide, an expression vector comprising this polynucleotide, a cell transfected with the expression vector, an antibody binding to the above polypeptide, a convenient screening method for obtaining an agent for treating joint diseases, and a process for manufacturing a pharmaceutical composition for treating joint diseases are disclosed.
    Type: Application
    Filed: October 2, 2002
    Publication date: October 2, 2003
    Inventors: Noboru Yamaji, Kouichi Nishimura, Kunitake Abe
  • Patent number: 6608577
    Abstract: In a digital/analog converter, a digital-to-analog converting section includes a constant current source circuit having a plurality of binary-coding weighted current output terminals and including a plurality of MOS transistor type current switches driven by digital input signals. Each of the MOS transistor type current switches is connected between one of the binary-coding weighted current terminals and an analog output current terminal. A reference voltage generating section generates at least one reference voltage and supplies it to the constant current source circuit. A current-to-voltage converting section converts an analog output current flowing through the analog output current terminal into an analog output voltage in response to the analog output current and supplies the analog output voltage to an analog output voltage terminal.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: August 19, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Kouichi Nishimura
  • Publication number: 20030129658
    Abstract: A novel polypeptide, a polynucleotide encoding the polypeptide, an expression vector comprising the polynucleotide, a cell transfected with the expression vector, an antibody or a fragment thereof binding to the polypeptide, and a process for producing the polypeptide are disclosed.
    Type: Application
    Filed: November 26, 2002
    Publication date: July 10, 2003
    Inventors: Noboru Yamaji, Kouichi Nishimura, Kunitake Abe, Makoto Ogino
  • Publication number: 20020008653
    Abstract: In a digital/analog converter, a digital-to-analog converting section includes a constant current source circuit having a plurality of binary-coding weighted current output terminals and including a plurality of MOS transistor type current switches driven by digital input signals. Each of the MOS transistor type current switches is connected between one of the binary-coding weighted current terminals and an analog output current terminal. A reference voltage generating section generates at least one reference voltage and supplies it to the constant current source circuit. A current-to-voltage converting section converts an analog output current flowing through the analog output current terminal into an analog output voltage in response to the analog output current and supplies the analog output voltage to an analog output voltage terminal.
    Type: Application
    Filed: June 26, 2001
    Publication date: January 24, 2002
    Inventor: Kouichi Nishimura
  • Publication number: 20010004255
    Abstract: A liquid crystal display driving circuit is provided with a first amplifier unit, a second amplifier unit, a first bias voltage source, a second bias voltage source, and a bias switch. The first amplifier unit receives a &ggr; corrected negative type image signal or a &ggr; corrected positive type image signal. The second amplifier unit receives the positive type image signal when the first amplifier unit receives the negative type image signal or the negative type image signal when the first amplifier unit receives the positive type image signal. The first bias voltage source generates a first bias voltage. The second bias voltage source generates a second bias voltage. The bias switch applies the first bias voltage to the first amplifier unit when the second bias voltage is applied to second amplifier unit or the second bias voltage to the first amplifier unit when the first bias voltage is applied to the second amplifier unit.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 21, 2001
    Applicant: NEC Corporation
    Inventor: Kouichi Nishimura
  • Patent number: 6229371
    Abstract: The present invention makes it possible to prevent feedback loops from causing oscillations in clamp circuits. When a video signal is input through a capacitor into a first inverting input terminal of an operational amplifier, the output terminal tends to reach a high level because the potential of the first inverting input terminal is lower than the potential of the non-inverting input terminal to which the black level reference signal is input. Thereby the NPN transistor whose base is connected to the output terminal is turned on to charge the capacitor. When the charging of the capacitor approaches completion, the potential of the first inverting input terminal becomes higher than the potential of the second inverting input terminal.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: May 8, 2001
    Assignee: NEC Corporation
    Inventors: Kouichi Nishimura, Yoshihiko Hori
  • Patent number: 6075505
    Abstract: An active matrix liquid crystal display is provided, wherein adjacent two odd and even pixels are commonly connected to a single signal line, and two scanning lines are allocated to one horizontal display line, two switching elements of the adjacent two odd and even pixels are respectively connected to different ones of the two scanning lines and further the odd and even display lines are opposite to each other in connections of the display lines and the switching elements.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventors: Hiroshi Shiba, Koichi Koga, Kouichi Nishimura
  • Patent number: 5987895
    Abstract: Molded bodies of a hydrogen absorbing alloy accommodated in a hydrogen storage container are made readily replaceable to ensure stabilized supply of hydrogen gas. When exhibiting an impaired hydrogen absorbing-desorbing capacity, the molded bodies can be easily replaced by new molded bodies, whereby a specified hydrogen absorbing-desorbing capacity can be maintained. The hydrogen gas released from the storage container is partly utilized to heat the container and thereby maintain the alloy at a predetermined temperature, consequently assuring a device, such as a fuel cell, of stabilized supply of hydrogen from the container.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: November 23, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kouichi Nishimura, Kouichi Satoh, Shin Fujitani, Ikuo Yonezu, Koji Nishio