Patents by Inventor Kouji Matsuo
Kouji Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220352188Abstract: A semiconductor memory device includes a first semiconductor layer, first conductive layers, electric charge accumulating portions, a first conductivity-typed second semiconductor layer, a first wiring, a second conductivity-typed third semiconductor layer, and a second conductive layer. The first semiconductor layer extends in a first direction. First conductive layers are arranged in the first direction and extend in a second direction. Electric charge accumulating portions are disposed between the first semiconductor layer and first conductive layers. The second semiconductor layer is connected to one end of the first semiconductor layer. The first wiring is connected to the first semiconductor layer via the second semiconductor layer. The third semiconductor layer is connected to a side surface in a third direction of the first semiconductor layer. The second conductive layer extends in the second direction and is connected to the first semiconductor layer via the third semiconductor layer.Type: ApplicationFiled: March 11, 2022Publication date: November 3, 2022Applicant: Kioxia CorporationInventors: Ryo FUKUOKA, Fumitaka ARAI, Kouji MATSUO, Hiroaki KOSAKO, Keiji HOSOTANI, Takayuki KAKEGAWA, Shinya NAITO, Shinji MORI
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Publication number: 20220310647Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor extending in a first direction parallel to a substrate; a first conductor extending in a second direction perpendicular to the first direction; a first charge storage layer surrounding the first conductor; a first insulator provided between the first conductor and the first charge storage layer; a second insulator provided between the first charge storage layer and the first semiconductor, wherein an outer circumference of a portion of the second insulator is in contact with the first semiconductor; and a first memory cell including the first conductor, the first semiconductor, a portion of the first charge storage layer, a portion of the first insulator, and the portion of the second insulator.Type: ApplicationFiled: September 3, 2021Publication date: September 29, 2022Inventor: Kouji MATSUO
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Publication number: 20220302016Abstract: A semiconductor memory device includes memory block regions arranged in a first direction, a hook-up region arranged in the first direction with respect to memory block regions, and a wiring region extending in the first direction and arranged with memory block regions and the hook-up region in a second direction. Each of memory block regions includes memory strings extending in the first direction and arranged in the second direction and a first wiring extending in the second direction and connected to memory strings in common. The wiring region includes a second wiring extending in the first direction and connected to first wirings corresponding to memory block regions in common. The hook-up region includes a third wiring connected to the second wiring and a contact electrode extending in a third direction and connected to the third wiring.Type: ApplicationFiled: September 10, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Kouji MATSUO, Fumitaka ARAI
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Publication number: 20220065341Abstract: The gear mechanism includes a gear shaped to have a bottom land, a first tooth flank connected to the bottom land, a second tooth flank connected to the bottom land, a first tooth face connected to the first tooth flank, and a second tooth face connected to the second tooth flank. The bottom land is curved, a radius of curvature of the first tooth flank is greater than a radius of curvature of the second tooth flank, and parts of the first tooth flank and the second tooth flank connected to connection points with the bottom land are curved such that a distance of each of the parts from a shaft center of the gear decreases toward the connection points and that a gradient of each of the parts decreases toward the connection points.Type: ApplicationFiled: July 13, 2021Publication date: March 3, 2022Applicant: JATCO LtdInventors: Daiki KAMATA, Kouji MATSUO, Ryouhei SAITOU, Kunihiko FUKANOKI
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Patent number: 11217745Abstract: According to one embodiment, a method for manufacturing a magnetoresistive memory device includes forming a first layer stack on a substrate. A second layer stack including a first ferromagnet is formed on the first layer stack. A mask including a first portion and an opening is formed above the second layer stack. The second layer stack is etched with an ion beam that travels through the opening. The first layer stack is etched by reactive ion etching through the opening.Type: GrantFiled: March 13, 2019Date of Patent: January 4, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuichi Ito, Kouji Matsuo
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Publication number: 20210296585Abstract: A switching device in an embodiment includes: a first electrode; a second electrode, and a switching layer disposed between the first electrode and the second electrode. The switching layer is made of a material containing hafnium nitride. Otherwise, the switching layer is made of a material containing bismuth and at least one selected from the group consisting of silicon oxide, aluminum oxide, zirconium oxide, and gallium oxide, or a material containing at least one selected from the group consisting of bismuth oxide, bismuth nitride, bismuth boride, and bismuth sulfide.Type: ApplicationFiled: September 14, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Tadaomi DAIBOU, Hiroki KAWAI, Katsuyoshi KOMATSU, Weidong LI, Shogo ITAI, Kouji MATSUO
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Publication number: 20210247339Abstract: A ceramic member unit includes at least insertion members and a ceramic member having insertion sections into which the insertion members are inserted respectively. Each of the insertion sections has at least an insertion opening which opens on a deeper side of an introduction opening in the surface of the ceramic member while communicating with the introduction opening and into which the insertion member can be inserted. The insertion section further has taper hole portions becoming narrower toward the insertion opening in a communication region between the introduction opening and the insertion opening. The taper hole portions are connected to the insertion opening while increasing in a taper angle toward the insertion opening.Type: ApplicationFiled: February 8, 2019Publication date: August 12, 2021Applicant: NGK SPARK PLUG CO., LTD.Inventors: Masana OKAI, Kouji MATSUO, Daisuke TAHIRA
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Patent number: 11011700Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.Type: GrantFiled: March 16, 2020Date of Patent: May 18, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kouji Matsuo, Ryo Fukuoka, Yuta Yamada
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Publication number: 20200220076Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.Type: ApplicationFiled: March 16, 2020Publication date: July 9, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kouji MATSUO, Ryo FUKUOKA, Yuta YAMADA
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Patent number: 10629810Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.Type: GrantFiled: September 5, 2018Date of Patent: April 21, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kouji Matsuo, Ryo Fukuoka, Yuta Yamada
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Publication number: 20200098571Abstract: A storage device includes a crystalline silicon substrate, a stacked film including a plurality of crystalline silicon films provided on the crystalline silicon substrate and extending parallel to a crystalline silicon substrate surface and a plurality of insulating films extending parallel to the crystalline silicon substrate surface between the respective crystalline silicon films, a plurality of first conductive layers each having a disconnected end portion penetrating at least a portion of the stacked film and located below the stacked film, memory cells provided respectively between the plurality of crystalline silicon films and the plurality of first conductive layers, and a plurality of second conductive layers electrically connected to the plurality of crystalline silicon films respectively.Type: ApplicationFiled: February 28, 2019Publication date: March 26, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Kouji MATSUO
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Publication number: 20200083443Abstract: According to one embodiment, a method for manufacturing a magnetoresistive memory device includes forming a first layer stack on a substrate. A second layer stack including a first ferromagnet is formed on the first layer stack. A mask including a first portion and an opening is formed above the second layer stack. The second layer stack is etched with an ion beam that travels through the opening. The first layer stack is etched by reactive ion etching through the opening.Type: ApplicationFiled: March 13, 2019Publication date: March 12, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yuichi ITO, Kouji MATSUO
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Patent number: 10546896Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.Type: GrantFiled: September 6, 2017Date of Patent: January 28, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Arayashiki, Kouji Matsuo
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Patent number: 10475851Abstract: According to one embodiment, a method of manufacturing a storage device comprises forming a state change layer on a substrate. The state change layer has first and second resistance states. The state change layer is switchable from one to the other of the first and second resistance states according to a magnitude of a voltage applied thereto. A conductor is formed on an upper surface of the state change layer. The conductor comprises carbon. An upper surface of the conductor is processed to reduce the roughness thereof. A first ferromagnetic material is then formed on the upper surface of the conductor. A nonmagnetic material is formed on an upper surface of the first ferromagnetic material. A second ferromagnetic material is formed on an upper surface of the nonmagnetic material.Type: GrantFiled: August 31, 2018Date of Patent: November 12, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuichi Ito, Kouji Matsuo
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Publication number: 20190296233Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.Type: ApplicationFiled: September 5, 2018Publication date: September 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kouji MATSUO, Ryo FUKUOKA, Yuta YAMADA
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Publication number: 20190296078Abstract: According to one embodiment, a method of manufacturing a storage device comprises forming a state change layer on a substrate. The state change layer has first and second resistance states. The state change layer is switchable from one to the other of the first and second resistance states according to a magnitude of a voltage applied thereto. A conductor is formed on an upper surface of the state change layer. The conductor comprises carbon. An upper surface of the conductor is processed to reduce the roughness thereof. A first ferromagnetic material is then formed on the upper surface of the conductor. A nonmagnetic material is formed on an upper surface of the first ferromagnetic material. A second ferromagnetic material is formed on an upper surface of the nonmagnetic material.Type: ApplicationFiled: August 31, 2018Publication date: September 26, 2019Inventors: Yuichi ITO, Kouji MATSUO
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Patent number: 10319730Abstract: A memory device according to an embodiment includes: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film and having one end electrically connected to the first electrode and another end not connected and positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode provType: GrantFiled: March 21, 2018Date of Patent: June 11, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kouji Matsuo
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Publication number: 20190096900Abstract: A memory device according to an embodiment includes: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film and having one end electrically connected to the first electrode and another end not connected and positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode provType: ApplicationFiled: March 21, 2018Publication date: March 28, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Kouji MATSUO
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Patent number: 10211166Abstract: According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer.Type: GrantFiled: September 5, 2017Date of Patent: February 19, 2019Assignee: Toshiba Memory CorporationInventor: Kouji Matsuo
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Publication number: 20180277597Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.Type: ApplicationFiled: September 6, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yusuke ARAYASHIKI, Kouji MATSUO