Abstract: A ceramic member unit includes at least insertion members and a ceramic member having insertion sections into which the insertion members are inserted respectively. Each of the insertion sections has at least an insertion opening which opens on a deeper side of an introduction opening in the surface of the ceramic member while communicating with the introduction opening and into which the insertion member can be inserted. The insertion section further has taper hole portions becoming narrower toward the insertion opening in a communication region between the introduction opening and the insertion opening. The taper hole portions are connected to the insertion opening while increasing in a taper angle toward the insertion opening.

Abstract: A semiconductor memory device includes first memory layers and second memory layers arranged in alternation in a first direction. First memory layers and second memory layers include memory strings and first wirings connected to these memory strings in common. First memory layers and second memory layers include: signal amplifier circuits electrically connected to the first wirings; second wirings connected to the signal amplifier circuits; first switch transistors connected to the second wirings; third wirings electrically connected to the second wirings via the first switch transistors; and fourth wirings electrically connected to the second wirings without via the first switch transistors. The semiconductor memory device includes: first via-contact electrodes extending in the first direction and connected to the third wirings in first memory layers; and second via-contact electrodes extending in the first direction and connected to the fourth wirings in second memory layers.

Abstract: A semiconductor memory device includes a memory cell array and a peripheral circuit. The peripheral circuit includes a plurality of first nodes disposed corresponding to a plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address select circuit that electrically conducts one of the plurality of first nodes with the charging circuit or the discharging circuit in response to an input address signal, a plurality of first transistors each disposed in a current path between two of the plurality of first nodes, and a plurality of amplifier circuits that are disposed corresponding to the plurality of first via electrodes and include input terminals connected to any of the plurality of first nodes and output terminals connected to any of the plurality of first via electrodes.

Abstract: A semiconductor memory device includes a first semiconductor layer, first conductive layers, electric charge accumulating portions, a first conductivity-typed second semiconductor layer, a first wiring, a second conductivity-typed third semiconductor layer, and a second conductive layer. The first semiconductor layer extends in a first direction. First conductive layers are arranged in the first direction and extend in a second direction. Electric charge accumulating portions are disposed between the first semiconductor layer and first conductive layers. The second semiconductor layer is connected to one end of the first semiconductor layer. The first wiring is connected to the first semiconductor layer via the second semiconductor layer. The third semiconductor layer is connected to a side surface in a third direction of the first semiconductor layer. The second conductive layer extends in the second direction and is connected to the first semiconductor layer via the third semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor extending in a first direction parallel to a substrate; a first conductor extending in a second direction perpendicular to the first direction; a first charge storage layer surrounding the first conductor; a first insulator provided between the first conductor and the first charge storage layer; a second insulator provided between the first charge storage layer and the first semiconductor, wherein an outer circumference of a portion of the second insulator is in contact with the first semiconductor; and a first memory cell including the first conductor, the first semiconductor, a portion of the first charge storage layer, a portion of the first insulator, and the portion of the second insulator.

Abstract: A semiconductor memory device includes memory block regions arranged in a first direction, a hook-up region arranged in the first direction with respect to memory block regions, and a wiring region extending in the first direction and arranged with memory block regions and the hook-up region in a second direction. Each of memory block regions includes memory strings extending in the first direction and arranged in the second direction and a first wiring extending in the second direction and connected to memory strings in common. The wiring region includes a second wiring extending in the first direction and connected to first wirings corresponding to memory block regions in common. The hook-up region includes a third wiring connected to the second wiring and a contact electrode extending in a third direction and connected to the third wiring.

Abstract: The gear mechanism includes a gear shaped to have a bottom land, a first tooth flank connected to the bottom land, a second tooth flank connected to the bottom land, a first tooth face connected to the first tooth flank, and a second tooth face connected to the second tooth flank. The bottom land is curved, a radius of curvature of the first tooth flank is greater than a radius of curvature of the second tooth flank, and parts of the first tooth flank and the second tooth flank connected to connection points with the bottom land are curved such that a distance of each of the parts from a shaft center of the gear decreases toward the connection points and that a gradient of each of the parts decreases toward the connection points.

Abstract: According to one embodiment, a method for manufacturing a magnetoresistive memory device includes forming a first layer stack on a substrate. A second layer stack including a first ferromagnet is formed on the first layer stack. A mask including a first portion and an opening is formed above the second layer stack. The second layer stack is etched with an ion beam that travels through the opening. The first layer stack is etched by reactive ion etching through the opening.

Abstract: A switching device in an embodiment includes: a first electrode; a second electrode, and a switching layer disposed between the first electrode and the second electrode. The switching layer is made of a material containing hafnium nitride. Otherwise, the switching layer is made of a material containing bismuth and at least one selected from the group consisting of silicon oxide, aluminum oxide, zirconium oxide, and gallium oxide, or a material containing at least one selected from the group consisting of bismuth oxide, bismuth nitride, bismuth boride, and bismuth sulfide.

Abstract: A ceramic member unit includes at least insertion members and a ceramic member having insertion sections into which the insertion members are inserted respectively. Each of the insertion sections has at least an insertion opening which opens on a deeper side of an introduction opening in the surface of the ceramic member while communicating with the introduction opening and into which the insertion member can be inserted. The insertion section further has taper hole portions becoming narrower toward the insertion opening in a communication region between the introduction opening and the insertion opening. The taper hole portions are connected to the insertion opening while increasing in a taper angle toward the insertion opening.

Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.

Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.

Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.

Abstract: A storage device includes a crystalline silicon substrate, a stacked film including a plurality of crystalline silicon films provided on the crystalline silicon substrate and extending parallel to a crystalline silicon substrate surface and a plurality of insulating films extending parallel to the crystalline silicon substrate surface between the respective crystalline silicon films, a plurality of first conductive layers each having a disconnected end portion penetrating at least a portion of the stacked film and located below the stacked film, memory cells provided respectively between the plurality of crystalline silicon films and the plurality of first conductive layers, and a plurality of second conductive layers electrically connected to the plurality of crystalline silicon films respectively.

Abstract: According to one embodiment, a method for manufacturing a magnetoresistive memory device includes forming a first layer stack on a substrate. A second layer stack including a first ferromagnet is formed on the first layer stack. A mask including a first portion and an opening is formed above the second layer stack. The second layer stack is etched with an ion beam that travels through the opening. The first layer stack is etched by reactive ion etching through the opening.

Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.

Abstract: According to one embodiment, a method of manufacturing a storage device comprises forming a state change layer on a substrate. The state change layer has first and second resistance states. The state change layer is switchable from one to the other of the first and second resistance states according to a magnitude of a voltage applied thereto. A conductor is formed on an upper surface of the state change layer. The conductor comprises carbon. An upper surface of the conductor is processed to reduce the roughness thereof. A first ferromagnetic material is then formed on the upper surface of the conductor. A nonmagnetic material is formed on an upper surface of the first ferromagnetic material. A second ferromagnetic material is formed on an upper surface of the nonmagnetic material.

Abstract: A resistance-change type memory device includes a substrate, a plurality of electrodes arranged in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the upper surface, a resistance-change film provided in a third direction that is parallel to the upper surface and intersects the first direction as viewed from the plurality of electrodes, a semiconductor film provided between the plurality of electrodes and the resistance-change film, and an insulating film provided between the plurality of electrodes and the semiconductor film. The resistance-change film has a resistance value that changes when a current flows therein.

Abstract: According to one embodiment, a method of manufacturing a storage device comprises forming a state change layer on a substrate. The state change layer has first and second resistance states. The state change layer is switchable from one to the other of the first and second resistance states according to a magnitude of a voltage applied thereto. A conductor is formed on an upper surface of the state change layer. The conductor comprises carbon. An upper surface of the conductor is processed to reduce the roughness thereof. A first ferromagnetic material is then formed on the upper surface of the conductor. A nonmagnetic material is formed on an upper surface of the first ferromagnetic material. A second ferromagnetic material is formed on an upper surface of the nonmagnetic material.

Abstract: A memory device according to an embodiment includes: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film and having one end electrically connected to the first electrode and another end not connected and positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode prov