Patents by Inventor Kozo Makiyama

Kozo Makiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140312362
    Abstract: An embodiment of a compound semiconductor device includes: a substrate; a compound semiconductor stacked structure of nitride over the substrate; a passivation film that covers the compound semiconductor stacked structure; a gate electrode, a source electrode, and a drain electrode at a level above the compound semiconductor stacked structure; and an Si—C bond containing film that contains an Si—C bond and includes a part between the source electrode and the drain electrode. The part contacts at least a part of an upper surface of the compound semiconductor stacked structure or at least a part of an upper surface of the passivation film.
    Type: Application
    Filed: March 12, 2014
    Publication date: October 23, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Publication number: 20140306231
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 16, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, NAOYA OKAMOTO, Kozo Makiyama, Toshihiro Ohki
  • Publication number: 20140295666
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20140264826
    Abstract: A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive portion formed over a surface of the first insulating film, and a second insulating film which covers the principal plane of the substrate, the first insulating film, and the conductive portion and whose moisture resistance is higher than moisture resistance of the first insulating film. The first insulating film is placed between the substrate and the conductive portion to prevent the generation of parasitic capacitance. The first insulating film is covered with the second insulating film whose moisture resistance is higher than the moisture resistance of the first insulating film. The second insulating film prevents the first insulating film from absorbing moisture.
    Type: Application
    Filed: February 6, 2014
    Publication date: September 18, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Junichi Kon, Yoshihiro NAKATA, Kozo Makiyama
  • Patent number: 8816408
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure; a source electrode, a drain electrode, and a gate electrode formed over the compound semiconductor laminated structure; a first protective film formed over the compound semiconductor laminated structure between the source electrode and the gate electrode and including silicon; and a second protective film formed over the compound semiconductor laminated structure between the drain electrode and the gate electrode and including more silicon than the first protective film.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Toshihide Kikkawa
  • Patent number: 8791465
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20140197460
    Abstract: A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio.
    Type: Application
    Filed: December 3, 2013
    Publication date: July 17, 2014
    Applicant: Fujitsu Limited
    Inventor: Kozo Makiyama
  • Publication number: 20140197889
    Abstract: A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; a first insulating film covering the surface of the compound semiconductor stack structure; and a conductive film provided on the surface of the first insulating film.
    Type: Application
    Filed: November 25, 2013
    Publication date: July 17, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Publication number: 20140185347
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 3, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Patent number: 8709886
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20140091424
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer and has an opening formed thereon; and an electrode that fills the opening, that is brought into contact with the compound semiconductor layer, and that is formed on the protective insulating film, in which an orientation state of a contact portion between the electrode and the compound semiconductor layer and an orientation state of a contact portion between the electrode and the protective insulating film are the same.
    Type: Application
    Filed: July 16, 2013
    Publication date: April 3, 2014
    Inventor: Kozo MAKIYAMA
  • Publication number: 20140057401
    Abstract: A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa.
    Type: Application
    Filed: October 30, 2013
    Publication date: February 27, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Takahashi, Kozo Makiyama
  • Publication number: 20140045345
    Abstract: A protective insulation film covering a surface of a compound semiconductor region is formed to have a two-layer structure of a first insulation film and a second insulation film which have different properties. The first insulation film is a non-stoichiometric silicon nitride film while the second insulation film is a silicon nitride film in an almost stoichiometric state.
    Type: Application
    Filed: October 16, 2013
    Publication date: February 13, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Kozo MAKIYAMA
  • Publication number: 20140038372
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Application
    Filed: October 10, 2013
    Publication date: February 6, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Publication number: 20140016360
    Abstract: A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer; and a gate electrode formed on the protective insulating film, wherein the protective insulating film has a first trench and a second trench which is formed side by side with the first trench and in which the protective insulating film remains with only a predetermined thickness on the compound semiconductor layer, and wherein the gate electrode fills the first trench, and one end of the gate electrode is away from the first trench and located at least in the second trench.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 16, 2014
    Inventors: Kozo Makiyama, NAOYA OKAMOTO, Toshihide Kikkawa
  • Publication number: 20140008701
    Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.
    Type: Application
    Filed: September 15, 2013
    Publication date: January 9, 2014
    Applicant: FUJITSU LIMITED
    Inventors: NAOKO KURAHASHI, KOZO MAKIYAMA
  • Patent number: 8587092
    Abstract: A protective insulation film covering a surface of a compound semiconductor region is formed to have a two-layer structure of a first insulation film and a second insulation film which have different properties. The first insulation film is a non-stoichiometric silicon nitride film while the second insulation film is a silicon nitride film in an almost stoichiometric state.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 19, 2013
    Assignee: Fujitsu Limited
    Inventor: Kozo Makiyama
  • Patent number: 8581261
    Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Kozo Makiyama
  • Patent number: 8557645
    Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Limited
    Inventors: Naoko Kurahashi, Kozo Makiyama
  • Publication number: 20130082400
    Abstract: A HEMT has a compound semiconductor layer, a protection film which has an opening and covers an upper side of the compound semiconductor layer, and a gate electrode which fills the opening and has a shape riding on the compound semiconductor layer, wherein the protection film has a stacked structure of a lower insulating film not containing oxygen and an upper insulating film containing oxygen, and the opening includes a first opening formed in the lower insulating film and a second opening formed in the upper insulating film and wider than the first opening, the first opening and the second opening communicating with each other.
    Type: Application
    Filed: August 6, 2012
    Publication date: April 4, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Naoya Okamoto, Yuichi Minoura, Kozo Makiyama, Shirou Ozaki