Patents by Inventor Kozo Makiyama
Kozo Makiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
COMPOUND SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR COMPOUND SEMICONDUCTOR DEVICE, AND AMPLIFIER
Publication number: 20240039486Abstract: A manufacturing method for a compound semiconductor device, a semiconductor laminate structure, including an electron transit layer and an electron supply layer that are formed from compound semiconductor. A source electrode, a gate electrode, and a drain electrode are provided above the semiconductor laminate structure and arranged in a first direction. A first insulating film having a first internal stress is formed over the semiconductor laminate structure and between the gate electrode and the drain electrode. A slit extending in the first direction is defined in the first insulating film. An amplifier with a compensating circuit compensates distortion of an input signal of the semiconductor device.Type: ApplicationFiled: October 11, 2023Publication date: February 1, 2024Applicant: Fujitsu LimitedInventor: Kozo MAKIYAMA -
Patent number: 11791384Abstract: A semiconductor device includes an underlayer made of a first nitride semiconductor, a first buffer layer made of a second nitride semiconductor, provided on the underlayer, and subjected to compressive stress from the underlayer in an in-plane direction which is perpendicular to a thickness direction of the underlayer, a second buffer layer made of a third nitride semiconductor, provided on the first buffer layer, and subjected to compressive stress from the first buffer layer in the in-plane direction, a channel layer made of a fourth nitride semiconductor, provided on the second buffer layer, and subjected to compressive stress from the second buffer layer in the in-plane direction, and a barrier layer made of a fifth nitride semiconductor, and provided above the channel layer.Type: GrantFiled: March 23, 2021Date of Patent: October 17, 2023Assignee: FUJITSU LIMITEDInventors: Junya Yaita, Junji Kotani, Atsushi Yamada, Kozo Makiyama
-
Publication number: 20230275001Abstract: A semiconductor device includes a source electrode and a drain electrode located over a surface of a semiconductor layer including an electron transit layer and an electron supply layer. A gate electrode is located between the source electrode and the drain electrode. A first diamond layer is located between the source electrode and the drain electrode over the surface with an insulating film therebetween. A second diamond layer is located directly on the surface between the gate electrode and the drain electrode. Of heat generated by the semiconductor layer of the semiconductor device in operation, heat on the side of the electrode on which a relatively strong electric field is applied is efficiently transferred to the second diamond layer. The semiconductor device achieves an excellent heat dissipation property from the semiconductor layer and effectively suppresses overheating and a failure and degradation of the characteristics due to the overheating.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Applicant: FUJITSU LIMITEDInventors: Shirou OZAKI, Toshihiro OHKI, Kozo MAKIYAMA, Junya YAITA
-
Patent number: 11688663Abstract: A semiconductor device includes a source electrode and a drain electrode located over a surface of a semiconductor layer including an electron transit layer and an electron supply layer. A gate electrode is located between the source electrode and the drain electrode. A first diamond layer is located between the source electrode and the drain electrode over the surface with an insulating film therebetween. A second diamond layer is located directly on the surface between the gate electrode and the drain electrode. Of heat generated by the semiconductor layer of the semiconductor device in operation, heat on the side of the electrode on which a relatively strong electric field is applied is efficiently transferred to the second diamond layer. The semiconductor device achieves an excellent heat dissipation property from the semiconductor layer and effectively suppresses overheating and a failure and degradation of the characteristics due to the overheating.Type: GrantFiled: November 13, 2020Date of Patent: June 27, 2023Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Toshihiro Ohki, Kozo Makiyama, Junya Yaita
-
Patent number: 11646366Abstract: A disclosed semiconductor device includes an electron transit layer; an electron supply layer disposed above the electron transit layer; a source electrode, a drain electrode, and a gate electrode, the source electrode, the drain electrode, and the gate electrode being disposed on the electron supply layer; a first capping layer disposed on the electron supply layer between the gate electrode and the drain electrode; and a negative charge generation layer disposed on the first capping layer, the negative charge generation layer being configured to generate a negative charge.Type: GrantFiled: December 21, 2020Date of Patent: May 9, 2023Assignee: FUJITSU LIMITEDInventors: Kozo Makiyama, Shirou Ozaki, Atsushi Yamada, Junji Kotani
-
Publication number: 20220013642Abstract: A semiconductor device includes an underlayer made of a first nitride semiconductor, a first buffer layer made of a second nitride semiconductor, provided on the underlayer, and subjected to compressive stress from the underlayer in an in-plane direction which is perpendicular to a thickness direction of the underlayer, a second buffer layer made of a third nitride semiconductor, provided on the first buffer layer, and subjected to compressive stress from the first buffer layer in the in-plane direction, a channel layer made of a fourth nitride semiconductor, provided on the second buffer layer, and subjected to compressive stress from the second buffer layer in the in-plane direction, and a barrier layer made of a fifth nitride semiconductor, and provided above the channel layer.Type: ApplicationFiled: March 23, 2021Publication date: January 13, 2022Applicant: FUJITSU LIMITEDInventors: Junya YAITA, Junji KOTANI, Atsushi YAMADA, Kozo MAKIYAMA
-
Publication number: 20210384340Abstract: A disclosed semiconductor device includes a semiconductor stack structure having an electron transit layer and an electron supply layer, the electron transit layer and the electron supply layer being compound semiconductors; a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode, and the drain electrode being deposed above the electron supply layer; a first insulating film disposed on the semiconductor stack structure between the gate electrode and the source electrode, the first insulating film being positively charged and in direct contact with the semiconductor stack structure; and a second insulating film disposed on the semiconductor stack structure between the gate electrode and the drain electrode, the second insulating film being covalent and in direct contact with the semiconductor stack structure.Type: ApplicationFiled: March 2, 2021Publication date: December 9, 2021Applicant: FUJITSU LIMITEDInventors: Shirou Ozaki, Kozo Makiyama, Toshihiro Ohki
-
Patent number: 11094813Abstract: A compound semiconductor device includes a semiconductor multilayer structure including an electron transit layer and an electron supply layer of a compound semiconductor; a source electrode, a gate electrode, and a drain electrode that are disposed above the semiconductor multilayer structure and are aligned in a first direction; a first insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the drain electrode, and has a tensile stress; a second insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the source electrode, and has a compressive stress; and a protective film that is formed between the first insulating film and the semiconductor multilayer structure, and between the second insulating film and the semiconductor multilayer structure.Type: GrantFiled: January 3, 2020Date of Patent: August 17, 2021Assignee: FUJITSU LIMITEDInventor: Kozo Makiyama
-
Publication number: 20210234031Abstract: A disclosed semiconductor device includes an electron transit layer; an electron supply layer disposed above the electron transit layer; a source electrode, a drain electrode, and a gate electrode, the source electrode, the drain electrode, and the gate electrode being disposed on the electron supply layer; a first capping layer disposed on the electron supply layer between the gate electrode and the drain electrode; and a negative charge generation layer disposed on the first capping layer, the negative charge generation layer being configured to generate a negative charge.Type: ApplicationFiled: December 21, 2020Publication date: July 29, 2021Applicant: FUJITSU LIMITEDInventors: Kozo MAKIYAMA, Shirou OZAKI, Atsushi YAMADA, Junji KOTANI
-
Publication number: 20210225728Abstract: A semiconductor device includes a source electrode and a drain electrode located over a surface of a semiconductor layer including an electron transit layer and an electron supply layer. A gate electrode is located between the source electrode and the drain electrode. A first diamond layer is located between the source electrode and the drain electrode over the surface with an insulating film therebetween. A second diamond layer is located directly on the surface between the gate electrode and the drain electrode. Of heat generated by the semiconductor layer of the semiconductor device in operation, heat on the side of the electrode on which a relatively strong electric field is applied is efficiently transferred to the second diamond layer. The semiconductor device achieves an excellent heat dissipation property from the semiconductor layer and effectively suppresses overheating and a failure and degradation of the characteristics due to the overheating.Type: ApplicationFiled: November 13, 2020Publication date: July 22, 2021Applicant: FUJITSU LIMITEDInventors: Shirou OZAKI, Toshihiro Ohki, Kozo Makiyama, Junya Yaita
-
Publication number: 20210175330Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor over a substrate; a second semiconductor layer formed of a nitride semiconductor over the first semiconductor layer; a gate electrode formed over the second semiconductor layer; a source electrode and a drain electrode formed over the first semiconductor layer or the second semiconductor layer; a first region of an insulative film that is formed between the gate electrode and the source electrode over the second semiconductor layer, and contains positive charges; and a second region of the insulative film that is formed between the gate electrode and the drain electrode over the second semiconductor layer, and contains negative charges.Type: ApplicationFiled: October 23, 2020Publication date: June 10, 2021Applicant: FUJITSU LIMITEDInventor: Kozo Makiyama
-
Patent number: 11024730Abstract: A nitride semiconductor device includes a first nitride semiconductor layer; a back-barrier layer that contains InGaN provided on the first nitride semiconductor layer; and a second nitride semiconductor layer that is provided on the back-barrier layer, wherein, in the back-barrier layer, in a thickness direction, an In composition increases at a first interface with the first nitride semiconductor layer, and the In composition is continuously reduced toward a second interface with the second nitride semiconductor layer.Type: GrantFiled: March 7, 2019Date of Patent: June 1, 2021Assignee: FUJITSU LIMITEDInventor: Kozo Makiyama
-
Patent number: 10992269Abstract: A compound semiconductor device includes a first compound semiconductor layer containing a p-type impurity, a second compound semiconductor layer disposed over the first compound semiconductor layer and containing InGaN, an electron transit layer disposed over the second compound semiconductor layer, and an electron supply layer disposed over the electron transit layer.Type: GrantFiled: July 11, 2018Date of Patent: April 27, 2021Assignee: FUJITSU LIMITEDInventors: Tetsuro Ishiguro, Atsushi Yamada, Junji Kotani, Norikazu Nakamura, Kozo Makiyama
-
Patent number: 10964805Abstract: A compound semiconductor device includes a compound semiconductor laminate structure including an electron transit layer and an electron supply layer, a gate electrode, a source electrode, and a drain electrode that are formed over the electron supply layer, a first insulating layer of diamond formed between the gate electrode and the drain electrode over the compound semiconductor laminate structure, and a second insulating layer formed between the gate electrode and the source electrode over the compound semiconductor laminate structure, wherein a positive compressive stress is applied from the first insulating layer to the electron supply layer, and a compressive stress from the second insulating layer to the electron supply layer is smaller than the compressive stress from the first insulating layer to the electron supply layer.Type: GrantFiled: August 2, 2019Date of Patent: March 30, 2021Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Kozo Makiyama, Yuichi Minoura, Yusuke Kumazaki, Toshihiro Ohki, Naoya Okamoto
-
Patent number: 10916645Abstract: A compound semiconductor device includes: a compound semiconductor area including, at an upper most portion, a protective layer made of a compound semiconductor; and an ohmic electrode provided on the compound semiconductor area, the ohmic electrode being away from the protective layer in plan view and being not in contact with the protective layer.Type: GrantFiled: November 30, 2018Date of Patent: February 9, 2021Assignee: FUJITSU LIMITEDInventor: Kozo Makiyama
-
Patent number: 10804358Abstract: A compound semiconductor device includes: a compound semiconductor area in which a compound semiconductor plug is embedded and formed; and an ohmic electrode provided on the compound semiconductor plug, wherein the compound semiconductor plug includes, in a side surface portion that is as an interface with the compound semiconductor area, a high concentration dopant layer containing a dopant whose concentration is higher than that of other portions.Type: GrantFiled: November 16, 2018Date of Patent: October 13, 2020Assignee: FUJITSU LIMITEDInventors: Kozo Makiyama, Yuichi Minoura
-
Patent number: 10796917Abstract: A semiconductor device includes: a first semiconductor layer formed, on a substrate, of a nitride semiconductor; a second semiconductor layer formed, on the first semiconductor layer, of a nitride semiconductor; a source electrode formed on the second semiconductor layer; a drain electrode formed on the second semiconductor layer; a metal oxide film formed, between the source electrode and the drain electrode, on the second semiconductor layer; and a gate electrode formed on the metal oxide film. The metal oxide film includes AlOx and InOx. AlOx/InOx in the metal oxide film is greater than or equal to 3.Type: GrantFiled: April 16, 2019Date of Patent: October 6, 2020Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Kozo Makiyama, Naoya Okamoto
-
COMPOUND SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR COMPOUND SEMICONDUCTOR DEVICE, AND AMPLIFIER
Publication number: 20200251585Abstract: A compound semiconductor device includes a semiconductor laminate structure including an electron transit layer and an electron supply layer that are formed from compound semiconductor, a source electrode, a gate electrode, and a drain electrode that are provided above the semiconductor laminate structure and arranged in a first direction, and a first insulating film having a first internal stress and formed over the semiconductor laminate structure and between the gate electrode and the drain electrode, wherein a slit extending in the first direction is defined in the first insulating film.Type: ApplicationFiled: January 31, 2020Publication date: August 6, 2020Applicant: FUJITSU LIMITEDInventor: Kozo Makiyama -
Publication number: 20200251584Abstract: A compound semiconductor device includes a semiconductor multilayer structure including an electron transit layer and an electron supply layer of a compound semiconductor; a source electrode, a gate electrode, and a drain electrode that are disposed above the semiconductor multilayer structure and are aligned in a first direction; a first insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the drain electrode, and has a tensile stress; a second insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the source electrode, and has a compressive stress; and a protective film that is formed between the first insulating film and the semiconductor multilayer structure, and between the second insulating film and the semiconductor multilayer structure.Type: ApplicationFiled: January 3, 2020Publication date: August 6, 2020Applicant: FUJITSU LIMITEDInventor: Kozo Makiyama
-
Patent number: 10727305Abstract: A semiconductor device includes a nitride semiconductor stacked structure that includes a channel layer containing GaN and a barrier layer containing In and further includes a cap layer that contains GaN on the outermost surface but does not contain Al. The cap layer has a Ga/N ratio that varies along a thicknesswise direction.Type: GrantFiled: October 30, 2018Date of Patent: July 28, 2020Assignee: FUJITSU LIMITEDInventor: Kozo Makiyama