Abstract: A shipping container connector includes a first latch unit, a second latch unit and a pulling rope unit. The first latch unit has a first body member, a first latch portion. The first body member has two side walls cooperatively defining a mounting space. One of the side walls has a threading hole. The second latch unit is disposed in the mounting space, and includes a second body member, and a spring member. The pulling rope unit extends through the threading hole, and has an end fixed to the second latch unit, and an opposite end disposed outside of the threading hole. When the pulling rope unit is pulled, the second latch unit is driven to move relative to the first latch unit from a locked position to a released position, where the spring member accumulates a biasing force for biasing the second latch unit towards the locked position.

Abstract: A system includes at least one server and a power supply having multiple power supply units. After system boot-up, all power supply units in the power supply are turned on for supplying power to the at least one server. Next, the maximum output power value of the power supply and the conversion efficiency table containing the relationship between the loading rate and the conversion efficiency of the power supply are acquired, and the real-time conversion efficiency of the power supply is calculated. When it is determined based on the real-time conversion efficiency and the conversion efficiency table of the power supply that the power supply is not currently operating with an optimized conversion efficiency, one or more power supply units in the power supply are turned off or turned on according to a predetermined rule.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

Abstract: An immersion cooling system includes a cooling tank, a sensor and two control chips. The first control chip includes a first heartbeat circuit configured to periodically send a first heartbeat signal, a first watchdog circuit configured to real-time monitor the status of the first control circuit and a second heartbeat signal, a first data sensing port for selectively reading data measured by the sensor, and a first data transmitting port for selectively outputting data read by the first data sensing port. The second control chip includes a second heartbeat circuit configured to periodically send the second heartbeat signal, a second watchdog circuit configured to real-time monitor the status of the second control circuit and the first heartbeat signal, a second data sensing port for selectively reading data measured by the sensor, and a second data transmitting port for selectively outputting data read by the second data sensing port.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a first wafer and a second wafer as the first wafer includes a device wafer and the second wafer includes a blanket wafer, bonding the first wafer and the second wafer, performing a thermal treatment process to separate the second wafer into a first portion and a second portion, and then planarizing the first portion.

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

Abstract: An environment detecting module, for securing a shell of a server, includes a sensing module, configured to sense an environment status by a polling method and generate a sensing signal according to the environment status; a connection module, configured to electrically connect the environment detecting module to a host terminal with a first connection status or a second connection status; and a microcontroller unit, coupled to the sensing module and the connection module, configured to determine a power source of the environment detecting module according to the first connection status or the second connection status, and to determine a first mode or a second mode of the environment detecting module according to the power source.

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

Abstract: A lashing device includes: a base seat having a bottom wall, and two pivot lugs which cooperate with the bottom wall to define a pivot slot thereamong, and each of which is formed with an pivot hole communicating with the pivot slot; a pivot pin extending through the pivot hole of each of the pivot lugs; and an eye plate received in the pivot slot, and having a middle portion that is formed with a pivot hole provided for the pivot pin to movably extends therethrough, and first and second wing portions which are connected to opposite ends of the middle portion, respectively, and each of which has an elongated hole having an arc section. The arc axes of the arc sections of the elongated holes are aligned with the center axis of the pivot hole.

Abstract: An electronic apparatus and a hot-swappable storage device thereof are provided. The hot-swappable storage device includes a carrier, a connector, a controller, and a wireless communication interface. The carrier is configured to carry a plurality of storage components. The connector is configured to be electronically connected to a host end for performing a data transfer operation. The controller detects a connection status between the connector and the host end. The wireless communication interface decides whether to perform the data transfer operation according to the connection status.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.