Patents by Inventor Kuang Hsieh
Kuang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929431Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.Type: GrantFiled: April 24, 2023Date of Patent: March 12, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
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Publication number: 20240072097Abstract: A method for fabricating a semiconductor device includes the steps of providing a first wafer and a second wafer as the first wafer includes a device wafer and the second wafer includes a blanket wafer, bonding the first wafer and the second wafer, performing a thermal treatment process to separate the second wafer into a first portion and a second portion, and then planarizing the first portion.Type: ApplicationFiled: September 26, 2022Publication date: February 29, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
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Publication number: 20230335622Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
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Publication number: 20230299166Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai, Ching-Wen Hung, Chun-Hsien Lin
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Patent number: 11735646Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.Type: GrantFiled: November 6, 2020Date of Patent: August 22, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
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Publication number: 20230261102Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
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Patent number: 11729937Abstract: An environment detecting module, for securing a shell of a server, includes a sensing module, configured to sense an environment status by a polling method and generate a sensing signal according to the environment status; a connection module, configured to electrically connect the environment detecting module to a host terminal with a first connection status or a second connection status; and a microcontroller unit, coupled to the sensing module and the connection module, configured to determine a power source of the environment detecting module according to the first connection status or the second connection status, and to determine a first mode or a second mode of the environment detecting module according to the power source.Type: GrantFiled: September 27, 2021Date of Patent: August 15, 2023Assignee: Wiwynn CorporationInventors: Yi-Hao Chen, Cheng-Kuang Hsieh, Yung-Ti Chung, Jheng-Ying Jiang
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Patent number: 11705498Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.Type: GrantFiled: February 26, 2021Date of Patent: July 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai, Ching-Wen Hung, Chun-Hsien Lin
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Patent number: 11690452Abstract: A lashing device includes: a base seat having a bottom wall, and two pivot lugs which cooperate with the bottom wall to define a pivot slot thereamong, and each of which is formed with an pivot hole communicating with the pivot slot; a pivot pin extending through the pivot hole of each of the pivot lugs; and an eye plate received in the pivot slot, and having a middle portion that is formed with a pivot hole provided for the pivot pin to movably extends therethrough, and first and second wing portions which are connected to opposite ends of the middle portion, respectively, and each of which has an elongated hole having an arc section. The arc axes of the arc sections of the elongated holes are aligned with the center axis of the pivot hole.Type: GrantFiled: June 1, 2022Date of Patent: July 4, 2023Assignee: Formosa Forges CorporationInventor: Jung-Kuang Hsieh
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Patent number: 11681647Abstract: An electronic apparatus and a hot-swappable storage device thereof are provided. The hot-swappable storage device includes a carrier, a connector, a controller, and a wireless communication interface. The carrier is configured to carry a plurality of storage components. The connector is configured to be electronically connected to a host end for performing a data transfer operation. The controller detects a connection status between the connector and the host end. The wireless communication interface decides whether to perform the data transfer operation according to the connection status.Type: GrantFiled: July 3, 2020Date of Patent: June 20, 2023Assignee: Wiwynn CorporationInventors: Yi-Hao Chen, Cheng Kuang Hsieh
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Patent number: 11670710Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.Type: GrantFiled: December 7, 2021Date of Patent: June 6, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
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Publication number: 20230157029Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).Type: ApplicationFiled: December 13, 2021Publication date: May 18, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai, Chun-Hsien Lin
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Patent number: 11646367Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.Type: GrantFiled: December 7, 2021Date of Patent: May 9, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
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Publication number: 20230133713Abstract: A lashing device includes: a base seat having a bottom wall, and two pivot lugs which cooperate with the bottom wall to define a pivot slot thereamong, and each of which is formed with an pivot hole communicating with the pivot slot; a pivot pin extending through the pivot hole of each of the pivot lugs; and an eye plate received in the pivot slot, and having a middle portion that is formed with a pivot hole provided for the pivot pin to movably extends therethrough, and first and second wing portions which are connected to opposite ends of the middle portion, respectively, and each of which has an elongated hole having an arc section. The arc axes of the arc sections of the elongated holes are aligned with the center axis of the pivot hole.Type: ApplicationFiled: June 1, 2022Publication date: May 4, 2023Inventor: Jung-Kuang HSIEH
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Publication number: 20230014174Abstract: An environment detecting module, for securing a shell of a server, includes a sensing module, configured to sense an environment status by a polling method and generate a sensing signal according to the environment status; a connection module, configured to electrically connect the environment detecting module to a host terminal with a first connection status or a second connection status; and a microcontroller unit, coupled to the sensing module and the connection module, configured to determine a power source of the environment detecting module according to the first connection status or the second connection status, and to determine a first mode or a second mode of the environment detecting module according to the power source.Type: ApplicationFiled: September 27, 2021Publication date: January 19, 2023Applicant: Wiwynn CorporationInventors: Yi-Hao Chen, Cheng-Kuang Hsieh, Yung-Ti Chung, Jheng-Ying Jiang
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Publication number: 20220238677Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.Type: ApplicationFiled: February 26, 2021Publication date: July 28, 2022Inventors: Po-Kuang Hsieh, Shih-Hung Tsai, Ching-Wen Hung, Chun-Hsien Lin
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Publication number: 20220093783Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.Type: ApplicationFiled: December 7, 2021Publication date: March 24, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
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Publication number: 20220093782Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.Type: ApplicationFiled: December 7, 2021Publication date: March 24, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
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Patent number: 11227944Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.Type: GrantFiled: September 23, 2019Date of Patent: January 18, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
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Publication number: 20210357349Abstract: An electronic apparatus and a hot-swappable storage device thereof are provided. The hot-swappable storage device includes a carrier, a connector, a controller, and a wireless communication interface. The carrier is configured to carry a plurality of storage components. The connector is configured to be electronically connected to a host end for performing a data transfer operation. The controller detects a connection status between the connector and the host end. The wireless communication interface decides whether to perform the data transfer operation according to the connection status.Type: ApplicationFiled: July 3, 2020Publication date: November 18, 2021Applicant: Wiwynn CorporationInventors: Yi-Hao Chen, Cheng Kuang Hsieh