Abstract: Management methods for use in an electronic system having electronic devices and a host device in daisy-chain configuration are provided. The host device has a configuration setting. First, an arrangement sequence among the host device and the electronic devices is detected. Then, the configuration setting of the host device is adjusted according to the detected arrangement sequence of the host device and the electronic devices such that the host device uses the electronic devices to perform a specific operation corresponding to the detected arrangement sequence.

Abstract: Management methods for use in an electronic system having electronic devices and a host device in a daisy-chain configuration are provided. The Management method includes determining that the electronic system has a first connected combination when detecting that first electronic device and second electronic device have been connected with the host device; searching for a first set of software that are suitable for a combination of the first and second electronic devices according to the first connected combination; and installing or activating the first set of software that are suitable for a combination of the first and second electronic devices.

Abstract: A welding jig and welding process for planar magnetic components are provided. The welding jig includes a fixed piece and an elastic piece. The fixed piece includes a base and a carrier. The base has an opening, bumps at the bottom of the opening and a pair of operation ends extending from the opening. The carrier is fixed on the base and located in the opening, and has multiple through holes. When the bumps are located respectively in the through holes, an accommodation interval is formed between adjacent pairs of the bumps for the placement of the planar magnetic components. The elastic piece is secured to the fixed piece, and when the planar magnetic components are placed in the accommodation intervals of the fixed piece, the elastic piece covers the planar magnetic components and the planar magnetic components abut against two side edges of the elastic piece.

Abstract: An electric device with multiple data connection ports is provided. The electric device includes a body, a processing unit, and a detecting switch unit. The body includes M surfaces and N data connection ports disposed on the surfaces. The processing unit includes a first interface control unit and a second interface control unit. The detecting switch unit detects whether the data connection ports are connected. While detecting the ith and the jth data connection ports are connected, the detecting switch unit assigns the ith and the jth data connection ports to be controlled by the first interface control unit and the second interface control unit respectively, and disables the data connection ports other than the ith and the jth data connection ports. Thus, the electric device can connect to the other electric devices with the form of the data connection ports flexibility.

Abstract: A pendulum-type landslide monitoring system includes an outer tube for being implanted into a ground to be monitored; a plurality of measuring units, vertically aligned inside the outer tube for independently measuring displacement at different depths in the ground; a guiding tube inside the outer tube for a flexible image capturing device to pass therethrough; and a water-level monitoring tube installed in the outer tube. Thereby, the flexible image capturing device can capture data of the displacement obtained by the measuring units, for an operator to identify displacement of a sliding surface in the ground, and to visually observe images of flowing groundwater captured by the flexible image capturing device in the outer tube, in order to further determining groundwater flow patterns as well stratums in the ground.

Abstract: A fastener for securing a cargo container includes a hollow connector, a first pull rod, a second pull rod and an elastic element. The hollow connector includes first and second members provided with first and second bores, respectively, and a receiving cavity between the first and second end members. The first pull rod extends through the first bore into the cavity, while the second pull rod extends through the second bore into the cavity and has a retaining head attached thereto. The elastic element is disposed around the second pull rod between the second end member and the retaining head for biasing the retaining head to move away from the second end member. The receiving cavity is open to expose the elastic element and the retaining head. The fastener may further include a limiting unit to prevent distorted movement of, and a pressure-equalizing member to evenly distribute pressure on, the elastic element.

Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×10/cm?2, and methods for forming such memory cells.

Abstract: A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.

Abstract: Structures and methods to form a bistable resistive random access memory for reducing the amount of heat dissipation from electrodes by confining a heating region in the memory cell device are described. The heating region is confined in a kernel comprising a programmable resistive memory material that is in contact with an upper programmable resistive memory member and a lower programmable resistive memory member. The lower programmable resistive member has sides that align with sides of a bottom electrode comprising a tungsten plug. The lower programmable resistive member and the bottom electrode function a first conductor so that the amount of heat dissipation from the first conductor is reduced. The upper programmable resistive memory material and a top electrode function as a second conductor so that the amount of heat dissipation from the second conductor is reduced.

Abstract: A memory device includes first and second electrodes separated by an insulating member comprising upwardly and inwardly tapering surfaces connected by a surface segment. A bridge, comprising memory material, such as a phase change material, switchable between electrical property states by the application of energy, is positioned across the surface segment and in contact with the electrodes to define an inter-electrode path defined at least in part by the length of the surface segment. According to a method for making a memory cell device, the tapering surfaces may be created by depositing a dielectric material cap using a high density plasma (HDP) deposition procedure. The electrodes and the dielectric material cap may he planarized to create the surface segment on the dielectric material. At least one of the dielectric material depositing step and the planarizing step may be controlled so that the length of the surface and segment is within a chosen dimensional range, such as between 10 nm and 100 nm.

Abstract: The present invention discloses a power management architecture, the present invention comprises a user spacer located over a Kernel space, wherein the user space includes a PM (power management) aware application over a PM library having a PM manager; and the Kernel space having an interface over an APM daemon and device drivers, the APM daemon including a policy engine, a hardware located under the APM daemon and the device drivers.

Abstract: Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

Abstract: Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.

Abstract: An MRAM device comprises a plurality of MRAM structures, each MRAM structure comprising a magnetoresistive memory cell in close proximity to a high permeability conductive line and a single transistor configured to access the magnetoresistive memory cell for both read and write operations. The high permeability conductive line acts a current path for both read and write operations, thereby reducing the number of metal bit lines.

Abstract: A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void region. A memory material is in the void region in electrical contact with the electrode surface. A second electrode is in electrical contact with the memory material. Energy passing between the first and second electrodes is concentrated within the memory material so to facilitate changing an electrical property state of the memory material. The memory material may comprise a phase change material. The second material may comprise a high density plasma-deposited material. A method for making a memory cell device is also disclosed.

Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm?2, and methods for forming such memory cells.

Abstract: A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.

Abstract: Disclosed are various embodiments that program a memory array with different carrier movement processes. In one application, memory cells are programmed with a particular carrier movement process depending on the pattern of data usage, such as code flash and data flash. In another application, memory cells are programmed with a particular carrier movement process depending on particular threshold voltage state to be programmed, in a multi-level cell scheme.

Abstract: A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm?3 and an interface trap density of up to 5E11 cm?2 eV?1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.

Abstract: Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.