Patents by Inventor Kuang Hsieh

Kuang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070054449
    Abstract: Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.
    Type: Application
    Filed: August 23, 2005
    Publication date: March 8, 2007
    Inventors: Yen-Hao Shih, Shih-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Hsieh
  • Publication number: 20060280549
    Abstract: A fastener for securing a cargo container includes a hollow connector, a first pull rod, a second pull rod and an elastic element. The hollow connector includes first and second members provided with first and second bores, respectively, and a receiving cavity between the first and second end members. The first pull rod extends through the first bore into the cavity, while the second pull rod extends through the second bore into the cavity and has a retaining head attached thereto. The elastic element is disposed around the second pull rod between the second end member and the retaining head for biasing the retaining head to move away from the second end member. The receiving cavity is open to expose the elastic element and the retaining head. The fastener may further include a limiting unit to prevent distorted movement of, and a pressure-equalizing member to evenly distribute pressure on, the elastic element.
    Type: Application
    Filed: September 9, 2005
    Publication date: December 14, 2006
    Inventor: Jung-Kuang Hsieh
  • Publication number: 20060146614
    Abstract: A raised-Vs Channel Initialed Secondary Electron Injection is disclosed to program a charge-trapping nonvolatile memory cell. The source of the charge-trapping nonvolatile memory cell is applied with a positive source voltage, and the drain of the charge-trapping nonvolatile memory cell is applied with a positive drain voltage, wherein the positive drain voltage is greater than the positive source voltage. The substrate of the charge-trapping nonvolatile memory cell is grounded. A positive gate voltage is applied to the polysilicon gate of the charge-trapping nonvolatile memory cell.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Hang-Ting Lue, Kuang Hsieh
  • Publication number: 20050147763
    Abstract: A thin film on a deposition area of a wafer structure is formed of substantially parallel, substantially straight tracts of film material, adjacent ones of which partly overlap. Each tract has a lengthwise midline, and the thickness of film material and a section across each tract has a Gaussian or near-Gaussian profile with a maximum at the midline. The distance between midlines of adjacent tracts is in a range from 0.1 to 3 times a standard deviation.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 7, 2005
    Applicant: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Kuang Hsieh
  • Publication number: 20050074927
    Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 7, 2005
    Inventors: Kuang Hsieh, Keh-Yung Cheng, Kuo-Lih Chang, John Epple, Gregory Pickrell
  • Patent number: 6719930
    Abstract: A production method of a light guide and a stamper, combining anisotropic etching and isotropic etching. First a plurality of microstructures is formed on a back surface and a front surface of the substrate. By electroforming, rear and front stampers are made from the back and front surfaces of the substrate. Light guides are produced using the rear and front stampers. Anisotropic etching is performed on the front surface of the substrate, forming V-shaped, U-shaped or pyramid like microstructures. Isotropic etching is performed on the back surface of the substrate, forming quadratic, bowl like, oval or semicircular microstructures. If a transparent substrate is used, then after finishing the etching of microstructures, a light source, a reflector, a diffusion sheet and a prism sheet are added, simulating a back light module for performing a test of luminosity, uniformity of light intensity and light emission angle, so that optical properties are known before proceeding with inverse-forming of the stampers.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: April 13, 2004
    Assignee: Litek Opto-Electronics Co., Ltd.
    Inventors: Shih-Chou Chen, Chung-Kuang Hsieh, Chih-Han Fang, Yuh-Sheng Lin
  • Publication number: 20030020189
    Abstract: A production method of a light guide and a stamper, combining anisotropic etching and isotropic etching. First a plurality of microstructures is formed on a back surface and a front surface of the substrate. By electroforming, rear and front stampers are made from the back and front surfaces of the substrate. Light guides are produced using the rear and front stampers. Anisotropic etching is performed on the front surface of the substrate, forming V-shaped, U-shaped or pyramid like microstructures. Isotropic etching is performed on the back surface of the substrate, forming quadratic, bowl like, oval or semicircular microstructures. If a transparent substrate is used, then after finishing the etching of microstructures, a light source, a reflector, a diffusion sheet and a prism sheet are added, simulating a back light module for performing a test of luminosity, uniformity of light intensity and light emission angle, so that optical properties are known before proceeding with inverse-forming of the stampers.
    Type: Application
    Filed: July 24, 2001
    Publication date: January 30, 2003
    Inventors: Shih-Chou Chen, Chung-Kuang Hsieh, Chih-Han Fang, Yuh-Sheng Lin
  • Publication number: 20020144576
    Abstract: A production method for 3-dimensional microstructures, using a micro-cutting tool with cutting edges for working a surface of a work object and generating a 3-dimensional microstructure that is inverted to the cutting edges of the micro-cutting tool. Production of the micro-cutting tool is performed by generating a photoresist mold of equal shape on a substrate using photolithography, then electroplating in said photoresist mold. After that, the micro-cutting tool is vertically put on the work object, generating the 3-dimensional microstructure on the surface of the work object.
    Type: Application
    Filed: April 6, 2001
    Publication date: October 10, 2002
    Inventors: Shih-Chou Chen, Chung-Kuang Hsieh, Yuh-Sheng Lin