Abstract: According to an embodiment, a neural network device includes a plurality of cores, and a plurality of routers. Each of the plurality of routers includes an input circuit and an output circuit. Each of the plurality of cores transmits at least one of forward direction data propagating in the neural network in a forward direction and reverse direction data propagating in the neural network in a reverse direction. The input circuit receives the forward direction data and the reverse direction data from any one of the plurality of cores and the plurality of routers. The output circuit or the input circuit selectively deletes the reverse direction data stored based on a request signal for requesting reception of data.

Abstract: According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.

Abstract: According to an embodiment, a neural network device includes: a plurality of cores each executing computation and processing of a partial component in a neural network; and a plurality of routers transmitting data output from each core to one of the plurality of cores such that computation and processing are executed according to structure of the neural network. Each of the plurality of cores outputs at least one of a forward data and a backward data propagated through the neural network in a forward direction and a backward direction, respectively. Each of the plurality of routers is included in one of a plurality of partial regions each being a forward region or a backward region. A router included in the forward region and a router included in the backward region transmit the forward data and the backward data to other routers in the same partial regions, respectively.

Abstract: A memory device according to an embodiment can be used for storing weights for a neural network. An update circuit changes a difference between charge amounts accumulated in first/second accumulation circuits in the memory device. An output circuit outputs, as a weight, a signal corresponding to the difference between the charge amounts. The update circuit performs the change of the difference by changing, when the update amount is positive, the electric charges accumulated in the first accumulation circuit in a first direction by a charge amount corresponding to an absolute value of the update amount, the first direction being either an increasing direction or a decreasing direction, and changing, when the update amount is negative, the electric charges accumulated in the second accumulation circuit in the first direction by a charge amount corresponding to an absolute value of the update amount.

Abstract: To provide an electrocatalyst for fuel cells, which is configured to ensure both the initial performance and durability of fuel cells. An electrocatalyst for fuel cells, wherein the electrocatalyst comprises a carbon support including a mesopore and a catalyst alloy supported on the carbon support, and the catalyst alloy is a catalyst alloy of platinum and a transition metal; wherein the mesopore includes at least one throat; wherein an average effective diameter of the at least one throat is 1.8 nm or more and less than 3.2 nm; and wherein a transition metal ratio of the catalyst alloy supported on a deeper-side region than the at least one throat, is lower than the transition metal ratio of the catalyst alloy supported on a nearer-side region than the at least one throat.

Abstract: A synaptic circuit according to an embodiment is a circuit in which a weight value changed by learning is set. The synaptic circuit receives a binary input signal from a pre-synaptic neuron circuit and outputs an output signal to a post-synaptic neuron circuit. The synaptic circuit includes a propagation circuit and a control circuit. The propagation circuit supplies, to the post-synaptic neuron circuit, the output signal obtained by adding an influence of the weight value to the input signal. The control circuit stops output of the output signal from the propagation circuit to the post-synaptic neuron circuit when the weight value is smaller than a predetermined reference value.

Abstract: In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between. the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film. is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating. film and the second electrode film.

Abstract: A neural network device according to an embodiment includes an arithmetic circuit, a learning control circuit, and a bias reset circuit. The arithmetic circuit executes arithmetic processing according to a neural network using a plurality of weights each represented by a value of a first resolution and a plurality of biases each represented by a value in ternary. At the time of learning of the neural network, the learning control circuit repeats a learning process of updating each of the plurality of weights and each of the plurality of biases a plurality of times based on a result of the arithmetic processing according to the neural network performed by the arithmetic circuit. In each learning process, the bias reset circuit resets a bias randomly selected with a preset first probability among the plurality of biases to a median in the ternary.

Abstract: According to one embodiment, there is provided a neural network device including a neuron, a conversion part, a transmission part, a control part and a holding part. The conversion part converts a spike signal to a synapse current according to weight. The transmission part transmits the converted synapse current to the neuron. The control part determines transition of a state of the weight. The holding part holds the weight as a discrete state according to the determined transition of the state. The holding part includes an action part that stochastically operates based on a signal input from the control part to cause transition of the state of the weight. A cumulative probability of actions of the action part changes in a sigmoidal shape with respect to number of signal input times.

Abstract: A storage device according to an embodiment is for storing weights being continuous values. The storage device includes: a shift register, an initialization circuit, an update control circuit, and a readout control circuit. The shift resistor includes a plurality of cells, each being arranged in series and storing information. A position of each of the plurality of cells corresponds to the weight. The initialization circuit writes the information to a cell in the shift register. The update control circuit shifts a position of the cell storing the information in a direction corresponding to a sign of an update amount by a number of cells corresponding to an absolute value of the update amount. The readout control circuit reads out the information and outputs an output value according to the weight corresponding to the position of the cell storing the information.

Abstract: An arithmetic device includes N product-sum-operation circuits, a control circuit, and an output circuit. Each product-sum-operation circuit outputs intermediate signals obtained by binarizing a product-sum-operation value obtained by product-sum-operation of M input values of M input signals and M weight values. The control circuit inverts positive/negative of each M weight value at determining-timing when a given time elapses from input timing. Based on a delay time from the determination-timing to logic finalization of the intermediate signal for each N product-sum-operation circuit, the output circuit outputs an output signal representing a winner-product-sum-operation circuit for which the product-sum-operation value having a sign and the largest absolute value is calculated.

Abstract: A storage device according to an embodiment is for storing weights being continuous values. The storage device includes: a shift register, an initialization circuit, an update control circuit, and a readout control circuit. The shift resistor includes a plurality of cells, each being arranged in series and storing information. A position of each of the plurality of cells corresponds to the weight. The initialization circuit writes the information to a cell in the shift register. The update control circuit shifts a position of the cell storing the information in a direction corresponding to a sign of an update amount by a number of cells corresponding to an absolute value of the update amount. The readout control circuit reads out the information and outputs an output value according to the weight corresponding to the position of the cell storing the information.

Abstract: A synaptic circuit according to an embodiment includes: a weight current circuit that applies a weight current corresponding to a weight value; an input switch that switches whether or not to cause the weight current circuit to apply the weight current; a capacitor that includes a first terminal and a second terminal, the first terminal being given a constant voltage; an output circuit that outputs the output signal corresponding to a capacitor voltage; a charge adjustment circuit that decreases or increases charges accumulated in the capacitor by drawing, from the second terminal, a capacitor current corresponding to a current value of the weight current, or supplying the capacitor current to the second terminal; and a control circuit that switches whether or not to reduce a current having a predetermined current value from the capacitor current in accordance with the weight value.

Abstract: A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a determinator, a synaptic depressor, and a synaptic potentiator. The synaptic element has a variable weight and outputs, in response to input of a first spike signal, a synaptic signal having intensity adjusted in accordance with the weight. The neuron circuit outputs a second spike signal in a case where the synaptic signal is inputted and a predetermined firing condition for the synaptic signal is satisfied. The determinator determines whether or not the weight is to be updated on a basis of an output frequency of the second spike signal by the neuron circuit. The synaptic depressor performs depression operation for depressing the weight in a case where it is determined that the weight is to be updated. The synaptic potentiator performs potentiating operation for potentiating the weight.

Abstract: According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.

Abstract: Mesoporous carbon has a beaded structure in which primary particles with mesopores are linked. In the mesoporous carbon, an average primary particle size is 7 nm or more and 300 nm or less, a pore diameter is 2 nm or more and 10 nm or less, an average thickness of pore walls is 3 nm or more and 15 nm or less, a pore volume is 0.2 mL/g or more and 3.0 mL/g or less, and a tap density is 0.03 g/cm3 or more and 0.3 g/cm3 or less. In a polymer electrolyte fuel cell, the mesoporous carbon is used as a catalyst carrier for at least an air electrode catalyst layer. The mesoporous carbon can be obtained by impregnating mesoporous silica satisfying a predetermined condition with a carbon source, performing polymerization and carbonization, and removing a template.

Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.

Abstract: A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a synaptic potentiator, and a synaptic depressor. The synaptic element has a variable weight. The neuron circuit inputs a spike voltage having a magnitude adjusted in accordance with the weight of the synaptic element via the synaptic element, and fires when a predetermined condition is satisfied. The synaptic potentiator performs a potentiating operation for potentiating the weight of the synaptic element depending on input timing of the spike voltage and firing timing of the neuron circuit. The synaptic depressor performs a depression operation for depressing the weight of the synaptic element in accordance with a schedule independent from the input timing of the spike voltage and the firing timing of the neuron circuit.

Abstract: A calculation device includes: M coefficient storage units provided corresponding to the M coefficients, each of the M coefficient storage units including a positive-side coefficient and a negative-side coefficient representing a coefficient corresponding to a sign of a difference; M multiplication units provided corresponding to the M input values, each of the M multiplication units calculating a positive-side multiply value obtained by multiplying the positive-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value and a negative-side multiply value obtained by multiplying the negative-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value; and an output unit outputting an value according to a difference between a positive-side sum value obtained by summing the M positive-side multiplication values and a negative-side sum value obtained by summing the M

Abstract: According to an embodiment, a neural network apparatus includes a plurality of neuron circuits, each including an integration circuit, a firing circuit, and a secondary battery. The integration circuit is configured to output an integral signal obtained by integrating input signals. The firing circuit is configured to generate, in accordance with the integral signal, a pulse signal to be transmitted to the neuron circuit provided at a subsequent layer. The secondary battery is configured to supply the firing circuit with drive electric power used for generating the pulse signal.