Patents by Inventor Kumiko Nomura
Kumiko Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8680887Abstract: According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.Type: GrantFiled: March 13, 2012Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Abe, Shinichi Yasuda, Kumiko Nomura, Shinobu Fujita
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Publication number: 20130301345Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected.Type: ApplicationFiled: February 8, 2013Publication date: November 14, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroki NOGUCHI, Shinobu Fujita, Keiko Abe, Kumiko Nomura, Kazutaka Ikegami
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Patent number: 8578318Abstract: In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.Type: GrantFiled: July 30, 2012Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kumiko Nomura, Shinichi Yasuda, Shinobu Fujita, Keiko Abe, Tetsufumi Tanamoto, Kazutaka Ikegami, Masato Oda
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Publication number: 20130268795Abstract: According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.Type: ApplicationFiled: December 28, 2012Publication date: October 10, 2013Inventors: Kumiko NOMURA, Shinobu FUJITA, Keiko ABE, Kazutaka IKEGAMI, Hiroki NOGUCHI
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Publication number: 20130246818Abstract: According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed.Type: ApplicationFiled: February 21, 2013Publication date: September 19, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kumiko NOMURA, Shinobu FUJITA, Keiko ABE, Kazutaka IKEGAMI, Hiroki NOGUCHI
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Patent number: 8437187Abstract: In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.Type: GrantFiled: September 14, 2011Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Yasuda, Masato Oda, Kumiko Nomura, Keiko Abe, Shinobu Fujita
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Publication number: 20130055189Abstract: In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.Type: ApplicationFiled: July 30, 2012Publication date: February 28, 2013Inventors: Kumiko Nomura, Shinichi Yasuda, Shinobu Fujita, Keiko Abe, Tetsufumi Tanamoto, Kazutaka Ikegami, Masato Oda
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Publication number: 20120246412Abstract: According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.Type: ApplicationFiled: September 16, 2011Publication date: September 27, 2012Inventors: Kumiko NOMURA, Keiko ABE, Shinobu FUJITA
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Publication number: 20120235705Abstract: According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.Type: ApplicationFiled: March 13, 2012Publication date: September 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiko Abe, Shinichi Yasuda, Kumiko Nomura, Shinobu Fujita
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Publication number: 20120230105Abstract: In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.Type: ApplicationFiled: September 14, 2011Publication date: September 13, 2012Inventors: Shinichi YASUDA, Masato Oda, Kumiko Nomura, Keiko Abe, Shinobu Fujita
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Publication number: 20120233377Abstract: According to an embodiment, a cache system includes a volatile cache memory, a nonvolatile cache memory, an address decoder, and an evacuation unit. The nonvolatile cache memory has a capacity equal to the volatile cache memory. The address decoder designates a same line to the volatile cache memory and the nonvolatile cache memory. The evacuation unit stores data which is inputted from the volatile cache memory and outputs the stored data to the volatile cache memory.Type: ApplicationFiled: September 16, 2011Publication date: September 13, 2012Inventors: Kumiko NOMURA, Keiko Abe, Shinobu Fujita
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Publication number: 20090217222Abstract: A semiconductor integrated circuit includes: a plurality of processor elements each including a test circuit which tests whether there is a failure in the processor element and outputs a result of the test; a plurality of switch boxes provided so as to be respectively associated with processor elements, each of the switch boxes configured to have a table to store information of another processor element and transmit information of a corresponding processor element to the other processor element based on information stored in the table; a plurality of identification circuits provided so as to be respectively associated with processor elements, each of the identification circuits configured to identify a defective processor element on the basis of the result of the test and output location information of the defective processor element; and a transmission circuit configured to transmit the location information of the defective processor element output from the identification circuit to the switch boxes.Type: ApplicationFiled: September 17, 2008Publication date: August 27, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinichi Yasuda, Kumiko Nomura, Keiko Abe
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Patent number: 7517830Abstract: In the distribution of surface vacancies which open on the surface of the cellular walls of pores, more than 8% of total opening area of all surface vacancies that the pores are open on the surface of the cellular walls is occupied by total opening area of surface vacancies having maximum diameter of from 10 to 50 ?m, in the distribution of inner pores, more than 20% of total cross-sectional area of all pores is occupied by total cross-sectional area of pores having cross-sectional area equivalent to that of a circle having diameter more than 300 ?m.Type: GrantFiled: February 13, 2004Date of Patent: April 14, 2009Assignee: Toyota Jidosha Kabushiki KaishaInventors: Kumiko Nomura, Satoko Inuduka
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Publication number: 20080243978Abstract: A random number generator includes an amplifier to amplify a difference between a noise signal and a reference signal to generate an amplified signal, a plurality of binarization circuits configured to binarize the amplified signal by using different inherent threshold values to obtain a plurality of binarized signals, and an exclusive OR circuit to perform an exclusive OR operation on the a plurality of binarized signals to generate random number sequence.Type: ApplicationFiled: March 17, 2008Publication date: October 2, 2008Inventors: Shinichi Yasuda, Keiko Abe, Tetsufumi Tanamoto, Kumiko Nomura
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Publication number: 20060154817Abstract: In the distribution of surface vacancies which open on the surface of the cellular walls of pores, more than 8% of total opening area of all surface vacancies that the pores are open on the surface of the cellular walls is occupied by total opening area of surface vacancies having maximum diameter of from 10 to 50 ?m measured by a direct observation method and, in the distribution of inner pores, more than 20% of total cross-sectional area of all pores is occupied by total cross-sectional area of pores having cross-sectional area equivalent to that of a circle having diameter more than 300 ?m measured by cross-sectional observation using CT scan. Even when a large amount of PMs are emitted densely at a short time, since they are dispersed and collected by each pore, PM deposition is controlled and the increase of the pressure loss is suppressed, as well as collecting efficiency is improved.Type: ApplicationFiled: February 13, 2004Publication date: July 13, 2006Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kumiko Nomura, Satoko Inuduka