Patents by Inventor Kumiko Nomura
Kumiko Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200302275Abstract: According to an embodiment, a neural network apparatus includes cores, routers, a tree path, and a short-cut path. The cores are provided according to leaves in a tree structure, each core serving as a circuit that performs calculation or processing for part of elements of the neural network. The routers are provided according to nodes other than the leaves in the tree structure. The tree path connects the cores and the routers such that data is transferred along the tree structure. The short-cut path connects part of the routers such that data is transferred on a route differing from the tree path. The routers transmit data output from each core to any of the cores serving as a transmission destination on one of routes in the tree path and the short-cut path such that the calculation or the processing is performed according to a structure of the neural network.Type: ApplicationFiled: September 9, 2019Publication date: September 24, 2020Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kumiko Nomura, Takao Marukame, Yoshifumi Nishi
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Publication number: 20200293861Abstract: According to an embodiment, an operation apparatus includes a first neural network, a second neural network, an evaluation circuit, and a coefficient-updating circuit. The first neural network performs an operation in a first mode. The second neural network performs an operation in a second mode and has a same layer structure as the first neural network. The evaluation circuit evaluates an error of the operation of the first neural network in the first mode and evaluates an error of the operation of the second neural network in the second mode. The coefficient-updating circuit updates, in the first mode, coefficients set for the second neural network based on an evaluating result of the error of the operation of the first neural network, and updates, in the second mode, coefficients set for the first neural network based on an evaluating result of the error of the operation of the second neural network.Type: ApplicationFiled: August 29, 2019Publication date: September 17, 2020Applicant: Kabushiki Kaisha ToshibaInventors: Takao MARUKAME, Yoshifumi Nishi, Kumiko Nomura
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Publication number: 20200090037Abstract: According to an embodiment, a neural network device includes: a plurality of cores each executing computation and processing of a partial component in a neural network; and a plurality of routers transmitting data output from each core to one of the plurality of cores such that computation and processing are executed according to structure of the neural network. Each of the plurality of cores outputs at least one of a forward data and a backward data propagated through the neural network in a forward direction and a backward direction, respectively. Each of the plurality of routers is included in one of a plurality of partial regions each being a forward region or a backward region. A router included in the forward region and a router included in the backward region transmit the forward data and the backward data to other routers in the same partial regions, respectively.Type: ApplicationFiled: March 12, 2019Publication date: March 19, 2020Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kumiko NOMURA, Takao MARUKAME, Yoshifumi NISHI
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Publication number: 20200034695Abstract: According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.Type: ApplicationFiled: February 27, 2019Publication date: January 30, 2020Applicant: Kabushiki Kaisha ToshibaInventors: Takao Marukame, Kumiko Nomura, Yoshifumi Nishi
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Publication number: 20200026496Abstract: A calculation device includes: M coefficient storage units provided corresponding to the M coefficients, each of the M coefficient storage units including a positive-side coefficient and a negative-side coefficient representing a coefficient corresponding to a sign of a difference; M multiplication units provided corresponding to the M input values, each of the M multiplication units calculating a positive-side multiply value obtained by multiplying the positive-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value and a negative-side multiply value obtained by multiplying the negative-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value; and an output unit outputting an value according to a difference between a positive-side sum value obtained by summing the M positive-side multiplication values and a negative-side sum value obtained by summing the MType: ApplicationFiled: March 7, 2019Publication date: January 23, 2020Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takao MARUKAME, Yoshifumi NISHI, Kumiko NOMURA
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Patent number: 10528270Abstract: A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.Type: GrantFiled: March 10, 2017Date of Patent: January 7, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Abe, Hiroki Noguchi, Susumu Takeda, Kumiko Nomura, Shinobu Fujita
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Publication number: 20200005130Abstract: According to an embodiment, a reinforcement learning system includes a memristor array in which each of a plurality of first direction lines corresponds to one of a plurality of states, and each of a plurality of second direction lines corresponds to one of a plurality of actions, a first voltage application unit that individually applies voltage to the first direction lines, a second voltage application unit that individually applies voltage to the second direction lines, a action decision circuit that decides action to be selected by an agent in a state corresponding to a first direction line to which a readout voltage is applied, a action storage unit that stores action selected by the agent in each state that can be caused in an environment, and a trace storage unit that stores a time at which the state is caused by action selected by the agent.Type: ApplicationFiled: March 4, 2019Publication date: January 2, 2020Applicant: Kabushiki Kaisha ToshibaInventors: Yoshifumi Nishi, Radu Berdan, Takao Marukame, Kumiko Nomura
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Publication number: 20190156180Abstract: According to an embodiment, a neural network device includes a plurality of cores, and a plurality of routers. Each of the plurality of routers includes an input circuit and an output circuit. Each of the plurality of cores transmits at least one of forward direction data propagating in the neural network in a forward direction and reverse direction data propagating in the neural network in a reverse direction. The input circuit receives the forward direction data and the reverse direction data from any one of the plurality of cores and the plurality of routers. The output circuit or the input circuit selectively deletes the reverse direction data stored based on a request signal for requesting reception of data.Type: ApplicationFiled: March 5, 2018Publication date: May 23, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Kumiko NOMURA, Takao Marukame
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Publication number: 20190156181Abstract: According to an embodiment, a neural network device includes a control unit, and a matrix computation unit. The control unit causes a plurality of layers to execute a forward process of propagating a plurality of signal values in a forward direction, and a backward process of propagating a plurality of error values in a backward direction. The matrix computation unit performs computation on a plurality of values propagated in the plurality of layers. The matrix computation unit includes (m×n) multipliers, and an addition circuit. The (m×n) multipliers are provided in one-to-one correspondence with (m×n) coefficients included in a coefficient matrix of m rows and n columns. The addition circuit switches a pattern for adding values output from the respective (m×n) multipliers between the forward process and the backward process.Type: ApplicationFiled: March 1, 2018Publication date: May 23, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Takao MARUKAME, Kumiko NOMURA
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Patent number: 10236062Abstract: According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.Type: GrantFiled: March 13, 2014Date of Patent: March 19, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Kazutaka Ikegami, Shinobu Fujita, Keiko Abe, Kumiko Nomura, Hiroki Noguchi
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Publication number: 20180081570Abstract: A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.Type: ApplicationFiled: March 10, 2017Publication date: March 22, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiko ABE, Hiroki NOGUCHI, Susumu TAKEDA, Kumiko NOMURA, Shinobu FUJITA
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Patent number: 9734061Abstract: A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.Type: GrantFiled: January 13, 2016Date of Patent: August 15, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kumiko Nomura, Shinobu Fujita, Keiko Abe, Kazutaka Ikegami, Hiroki Noguchi, Susumu Takeda
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Patent number: 9557801Abstract: According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed.Type: GrantFiled: February 21, 2013Date of Patent: January 31, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kumiko Nomura, Shinobu Fujita, Keiko Abe, Kazutaka Ikegami, Hiroki Noguchi
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Patent number: 9524764Abstract: According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps.Type: GrantFiled: October 1, 2013Date of Patent: December 20, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Hiroki Noguchi, Shinobu Fujita
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Publication number: 20160132430Abstract: A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.Type: ApplicationFiled: January 13, 2016Publication date: May 12, 2016Inventors: Kumiko Nomura, Shinobu Fujita, Keiko Abe, Kazutaka Ikegami, Hiroki Noguchi, Susumu Takeda
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Patent number: 9003128Abstract: According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.Type: GrantFiled: September 16, 2011Date of Patent: April 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kumiko Nomura, Keiko Abe, Shinobu Fujita
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Publication number: 20140379975Abstract: According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.Type: ApplicationFiled: March 13, 2014Publication date: December 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutaka IKEGAMI, Shinobu Fujita, Keiko Abe, Kumiko Nomura, Hiroki Noguchi
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Patent number: 8824199Abstract: According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected.Type: GrantFiled: February 8, 2013Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Noguchi, Shinobu Fujita, Keiko Abe, Kumiko Nomura, Kazutaka Ikegami
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Patent number: 8724403Abstract: According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.Type: GrantFiled: December 28, 2012Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kumiko Nomura, Shinobu Fujita, Keiko Abe, Kazutaka Ikegami, Hiroki Noguchi
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Publication number: 20140104920Abstract: According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps.Type: ApplicationFiled: October 1, 2013Publication date: April 17, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Hiroki Noguchi, Shinobu Fujita