Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.

Abstract: Embodiments of the disclosure provide systems and methods for generating text summarization. An exemplary system may include a processor and a non-transitory memory storing instructions that, when executed by the processor, cause the system to perform the various operations. The operations may include generating a document representation of a document. The document representation may include syntactic information. The operations may also include extracting salient information based on the document representation. The operations may further include generating a summary of the document based on the syntactic information and the salient information.

Abstract: Embodiments of the disclosure provide a multi-class classification system. An exemplary system includes at least one processor and at least one non-transitory memory storing instructions that, when executed by the at least one processor, cause the system to perform operations. The operation includes applying a multi-class classifier to classify a set of objects into multiple classes and applying a plurality of binary classifiers to the set of objects, wherein the plurality of binary classifiers are decomposed from the multi-class classifier, each binary classifier classifying the set of the objects into a first group consisting of one or more classes selected from the multiple classes and a second group consisting of one or more remaining classes of the multiple classes. The operation also includes jointly classifying the set of objects using the multi-class classifier and the plurality of binary classifiers.

Abstract: A method for manufacturing a golf club head having a weight member includes: providing a weight block made of a metal material; disposing an isolation layer on the weight block to form the weight member; delivering a wax material to form a wax pattern covering a portion of the weight member; coating the weight member and the wax pattern with a shell mold plaster to form a shell mold covering the same; performing a de-waxing process which leaves a mold cavity in the shell mold; and casting a molten metal material in the mold cavity to form a club head main body, and removing the shell mold to form the golf club head having the weight member embedded in the club head main body. A golf club head manufactured by the method is also disclosed.

Abstract: An online system receives a request to generate presentation content for presentation to a user. The online system receives a set of content items and identifies a surface for presenting the presentation information to the user. For example, the surface may be a voice only surface, a voice and graphical display, a graphical display only. Based on the identified surface, the online system ranks the set of content items. The online system then determines presentation information for a subset of the content items and transmits instructions to present the presentation information at the surface.

Abstract: The invention discloses a diaphragm and a sound generator having a diaphragm. The diaphragm includes a dome part arranged centrally and a suspension part surrounding the dome part. The suspension part is provided with pleat groups. The pleat group includes many pleats, and each pleats includes a first pattern section, a second pattern section, and a third pattern section connecting the first pattern section and the second pattern section. The height of the third pattern section along the vibration direction is smaller than the protrusion height of the first pattern section and the second pattern section along the vibration direction. The diaphragm of the present invention can be used to reduce low frequency distortion.

Abstract: A method for programming an electrically programmable fuse is disclosed. As conductive medium of the electrically programmable fuse exhibits different physical changes under different conditions, the conductive medium is changed from an initial physical state to a first physical state by using a first programming condition to program the electrically programmable fuse from a low resistance state to a medium resistance state, and the conductive medium is changed from the initial physical state or the first physical state to a second physical state by using a second programming condition to program the electrically programmable fuse from the low resistance state or the medium resistance state to a high resistance state. Transitions of three information storage states are achieved through two different programming conditions, so that the information storage density and chip area utilization rate of an electrically programmable fuse device can be significantly improved, and chip size reduction is facilitated.

Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a bonded semiconductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer can include a functional layer over a substrate. Single-crystalline silicon may not be essential to the substrate and the substrate may not include single-crystalline silicon. The first wafer can be flipped to bond onto the second wafer to form the bonded semiconductor device so the substrate is on top of the functional layer. At least a portion of the substrate can be removed to form a top surface of the bonded semiconductor device. Further, bonding pads can be formed over the top surface.

Abstract: A time dependent dielectric breakdown test structure includes a plurality of test units connected in parallel between a constant voltage and a ground. Each of the plurality of test units includes a dielectric test sample connected to the constant voltage; and a current restraint unit connected between the dielectric test sample and the ground, for restraining a breakdown current from flowing on the dielectric test sample after the constant voltage has broken the dielectric test sample.

Abstract: Disclosed is a panel testing device. The panel testing device includes: a supporter and a plurality of test pins disposed on the supporter, wherein the plurality of test pins are in one-to-one correspondence with a plurality of signal pins on the tested panel, any one of the test pins satisfies d?D?d+L; wherein D is a width of the test pin, d is a width of the signal pin corresponding to the test pin, L is a minimum pitch between two adjacent signal pins.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Abstract: A method for programming an electrically programmable fuse is disclosed. As conductive medium of the electrically programmable fuse exhibits different physical changes under different conditions, the conductive medium is changed from an initial physical state to a first physical state by using a first programming condition to program the electrically programmable fuse from a low resistance state to a medium resistance state, and the conductive medium is changed from the initial physical state or the first physical state to a second physical state by using a second programming condition to program the electrically programmable fuse from the low resistance state or the medium resistance state to a high resistance state. Transitions of three information storage states are achieved through two different programming conditions, so that the information storage density and chip area utilization rate of an electrically programmable fuse device can be significantly improved, and chip size reduction is facilitated.

Abstract: A computing device receives a message including a request for a recommendation. A representation of a hypothetical ideal recommendation to provide in response to the message is determined based on the message content. Data regarding entities that are potential recommendations are retrieved from a data store, the data regarding each entity including a representation of the entity (e.g., a vector) derived from factual information about the entity and opinions of other users of the entity. Ranking scores are determined for at least a subset of the entities based on the difference between the entity representations and the representation of the hypothetical ideal recommendation. An entity to recommend is selected based on the ranking scores and a reply to the message is sent that identifies the selected entity.

Abstract: An online system receives a request to generate presentation content for presentation to a user. The online system receives a set of content items and identifies a surface for presenting the presentation information to the user. For example, the surface may be a voice only surface, a voice and graphical display, a graphical display only. Based on the identified surface, the online system ranks the set of content items. The online system then determines presentation information for a subset of the content items and transmits instructions to present the presentation information at the surface.

Abstract: In one embodiment, a method includes receiving a user request for a summarization of a particular type of content objects from a client system associated with a first user, determining one or more modalities associated with the user request, selecting a plurality of content objects of the particular type based on a user profile of the first user, wherein the user profile comprises one or more confidence scores associated with one or more subjects associated with the first user, respectively, and wherein the plurality of content objects are selected based on the one or more confidence scores, generating a summary of each content object based on the user profile and the determined modalities, and sending, to the client system in response to the user request, instructions for presenting the summaries of the plurality of content objects, wherein the summaries are presented via one or more of the determined modalities.

Abstract: The present invention relates to a medical cast having a dual structure.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.

Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.

Abstract: Disclosed is a panel testing device. The panel testing device includes: a supporter and a plurality of test pins disposed on the supporter, wherein the plurality of test pins are in one-to-one correspondence with a plurality of signal pins on the tested panel, any one of the test pins satisfies d?D?d+L; wherein D is a width of the test pin, d is a width of the signal pin corresponding to the test pin, L is a minimum pitch between two adjacent signal pins.