Abstract: A power supply system with power factor correction, includes: an AC rectifier, a power factor correction (PFC) conversion circuit, an asymmetric half-bridge (AHB) flyback converter and a communication protocol power delivery (PD) interface. When a power level of an adapter output power is lower than a power threshold, and a converted voltage of a converted power is higher than a first voltage threshold, the communication protocol PD interface generates a disable signal to disable a PFC conversion of the PFC conversion circuit, when the PFC conversion is disabled, the PFC conversion circuit operates a bypass coupling operation, as thus, the converted voltage is equal to a rectified voltage of a rectified power.

Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.

Abstract: A resonant asymmetrical half-bridge flyback power converter includes: a first transistor and a second transistor switching a transformer coupled to a capacitor for generating an output power; a voltage divider coupled to an auxiliary winding of the transformer; a differential sensing circuit which includes a first terminal and a second terminal coupled to the voltage divider to sense an auxiliary signal generated by the auxiliary winding for generating a peak signal and a demagnetization-time signal; and a PWM control circuit configured to generate a first PWM signal and a second PWM signal in accordance with the peak signal and the demagnetization-time signal, for controlling the first transistor and the second transistor respectively; wherein a period of an enabling state of the demagnetization-time signal is correlated to the output power level; wherein the peak signal is related to a quasi-resonance of the transformer after the transformer is demagnetized.

Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.

Abstract: An electrophoresis display with gapped micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. Two adjacent partition walls have a gap therebetween and used as yielding space when the electrophoresis display is bent. The area of the gap is not larger than 50% of the area of the partition wall. Or the length of the gap is not longer than 50% of the length of the partition wall.

Abstract: An electrophoresis display double-side control circuit substrate includes a first control substrate having a first face and a second face, a first driving circuit layer and a first control electrode layer sequentially arranged on the second face, a second control substrate having a third face and a fourth face, a second driving circuit layer and a second control electrode layer sequentially arranged on the third face. The electrophoresis display includes a micro partition structure arranged between the first control substrate and the second control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution.

Abstract: An electrophoresis display with micro tenon includes a control substrate having a first face and a second face, a driving circuit layer and a control electrode layer sequentially arranged on the second face, an opposite substrate having a third face opposite to the second face and a fourth face, a micro partition structure formed between the second face and the third face. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The electrophoresis display further includes a plurality of micro tenons. Each of the micro tenons is corresponding to a face of the micro partition structure and embedded into one of the chambers.

Abstract: An electrophoresis display with improved micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The height of the partition wall of the micro partition structure is smaller than 25 um.

Abstract: An electrophoresis display includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The viewing face of the electrophoresis display is on the first face of the control substrate.

Abstract: An electrophoresis display with storage capacitor having transparent electrode includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of storage capacitors. At least the storage capacitors corresponding to the viewing area of the electrophoresis display have a transparent first electrode, a transparent second electrode and an insulating layer between the transparent first electrode and the transparent second electrode.

Abstract: An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The sum of the data line width and the gate line width is not larger than 10 ?m. The aperture ratio of the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 80%.

Abstract: An electrophoresis display with transparent control electrode includes a transparent control substrate having a first face and a second face, a driving circuit layer, a control electrode layer having a plurality of transparent control electrodes, an electrophoresis layer, and an opposite substrate. The charges of the transparent control electrodes attract the charged color particles with opposite polarity to the charges of the transparent control electrodes toward a face of the electrophoresis layer near the control electrodes, thus forming image for viewer.

Abstract: A color electrophoresis display with micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The electrophoresis display further includes a color filter layer arranged on bottom of the chamber. The colloidal solution contains charged black particles and/or charged white particles.

Abstract: An electrophoresis display includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The viewing face of the electrophoresis display is on the first face of the control substrate. The aperture ratio of the control substrate in the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 70%.

Abstract: An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The area of a semiconductor part of the TFT is at least partially overlapped with the area of one of the gate lines or the area of one of the date lines along a projection direction.

Abstract: An electrophoresis display with color filter structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The electrophoresis display further includes a color filter layer between the control substrate and the electrophoresis layer. The first face is the viewing face of the electrophoresis display.

Abstract: An electrophoresis display with embedded touch sensing includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer with electrophoresis material, and a touch with display driver (TDDI) electrically connected to data lines and common voltage lines. When the electrophoresis display performs touch sensing operation, the TDDI electrically connected plurality ones of the data lines into single a touch transmitting electrode or a single touch receiving electrode, and the TDDI electrically connected plurality ones of the common voltage lines into a single touch receiving electrode or a single touch transmitting electrode. The viewing face of the electrophoresis display is on the first face of the electrophoresis display.

Abstract: An electrophoresis display with tapered micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The sectional width of the partition wall decreases with a layer number of a polymer stacks forming the partition wall increases.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.