Patents by Inventor Kun Yu

Kun Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240109152
    Abstract: The invention relates to a combined dual-wavelength laser light processing device, having two laser light source and a Bessel beam lens, so as to form a Bessel beam with long focal length; Using the coaxial reflecting mirror to achieve deflecting and penetrating to form two coaxial finished light beams; a diffraction optical unit for adjusting the energy distribution of the finished light beam; a work platform; a laser galvanometric scanning module to achieve guiding the finished light beam; a controller electrically connected to the two laser light sources, and controls the projection timing and energy of the first and the second wavelength beams to form at least one rectangular pulse and at least one burst pulse, through the repeated conversion of the dual wavelengths in the composite light wave configuration make the processing of the composite material to be fast and precise.
    Type: Application
    Filed: April 19, 2023
    Publication date: April 4, 2024
    Inventors: Kun Yu Wu, Ming Tsung Tsai
  • Patent number: 11948340
    Abstract: An example apparatus for detecting objects in video frames includes a receiver to receive a plurality of video frames from a video camera. The apparatus also includes a first still image object detector to receive a first frame of the plurality of video frames and calculate localization information and confidence information for each potential object patch in the first frame. The apparatus further includes a second still image object detector to receive an adjacent frame of the plurality of video frames adjacent to the first frame and calculate localization information and confidence information for each potential object patch in the adjacent frame. The apparatus includes a similarity detector trained to detect paired patches between the first frame and the adjacent frame based on a comparison of the detected potential object patches.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kun Yu, Ciyong Chen, Xiaotian Guo, Yan Hao, Hui Li, Lu Li, Jianguo Pei, Zhi Yong Zhu
  • Patent number: 11929449
    Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2 ?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 12, 2024
    Assignees: SHANGHAI JINKO GREEN ENERGY ENTERPRISE MANAGEMENT CO., LTD., ZHEJIANG JINKO SOLAR CO., LTD.
    Inventors: Kun Yu, Changming Liu, Xinyu Zhang
  • Patent number: 11923360
    Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Yu Lee, Chun-Yao Wang, Chi On Chui
  • Publication number: 20240048046
    Abstract: A boost power factor correction circuit includes: a switch and an inductor coupled to each other; a current sensing device generating a current sensing signal according to a current flowing through the switch; a temperature sensing device coupled to the inductor to generate a temperature sensing signal; and a conversion control circuit operating the switch. The conversion control circuit is an integrated circuit and includes: a shared pin coupled to the temperature sensing device and the current sensing device; and a current sensing circuit and a temperature sensing circuit which sense a multipurpose sensing signal through the shared pin. The multipurpose sensing signal is related to the current sensing signal when the switch is ON and related to the temperature sensing signal when the switch is OFF. The temperature sensing signal is related to an input voltage, an output voltage and an electrical parameter of the temperature sensing device.
    Type: Application
    Filed: July 9, 2023
    Publication date: February 8, 2024
    Inventors: Shih-Ho Hsu, Kun-Yu Lin, Wei-Hsu Chang
  • Publication number: 20240030371
    Abstract: The present disclosure relates to a photovoltaic cell and a method for manufacturing a photovoltaic cell. The photovoltaic cell includes a substrate including an emitter and a passivation layer stacked in sequence on one side of the substrate. The emitter includes a first plane and a second plane laminated along a thickness direction of the emitter, and part of the emitter between the second plane and the first plane is a first doped layer. Within a unit volume, a rate of change ?C1 between doping concentration of the second plane and doping concentration of the first plane satisfies: ?C1?15%.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 25, 2024
    Inventors: Kun YU, Changming LIU, Xinyu ZHANG, Pengsong ZHAO, Dong WANG, Chao ZHOU
  • Publication number: 20240011916
    Abstract: A system for detecting a surface type of an object includes a driver component, a driver component, and a plurality of photosensitive elements. The surface of the object is divided along a first direction into a plurality of areas, and the driver component sequentially moves one of the plurality of areas to a detection position. The light source component faces the detection position and provides light of a plurality of spectra that are different from one another to illuminate the detection position. The photosensitive elements face different sections of the area at the detection position, to capture detection images of different sections of the area located at the detection position under the light of each of the spectra. One photosensitive axis of the photosensitive elements is parallel to the normal line while another photosensitive axis of the photosensitive elements is between the normal line and the first direction.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventor: Kun-Yu Tsai
  • Publication number: 20240014205
    Abstract: An input/output port circuit includes an input/output pad, a transistor, and a conductive routing wire. The transistor has a first connection terminal and a second connection terminal. The first connection terminal of the transistor is electrically connected to the input/output pad through a conductive connection wire, and the second connection terminal is electrically connected to another transistor. The conductive routing wire is electrically connected to the first terminal of the transistor. The conductive routing wire is configured to provide a serial resistance, thereby forcing a surge current to flow toward the another transistor when the surge current is inputted in the input/output circuit through the input/output pad.
    Type: Application
    Filed: September 9, 2022
    Publication date: January 11, 2024
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Sz-Ying YU, Chen-Hsuan KU, Shang-Hung LIN, Kun-Yu TAI
  • Publication number: 20240006550
    Abstract: Provided are a solar cell, including: a semiconductor substrate, in which a rear surface of the semiconductor substrate having non-pyramid-shaped microstructures, the non-pyramid-shaped microstructures include two or more first substructures at least partially stacked on one another, and a one-dimensional size of the surface of the outermost first substructure is less than or equal to 45 ?m; a first passivation layer located on a front surface of the semiconductor substrate; first and second tunnel oxide layers located on the non-pyramid-shaped microstructures; first and second doped conductive layers located on a surface of the first and second tunnel oxide layers, the first and second doped conductive layer has different conductive types; a second passivation layer located on a surface of the first and second doped conductive layers; and electrodes formed by penetrating through the second passivation layer to be in contact with the first and second doped conductive layers.
    Type: Application
    Filed: September 12, 2023
    Publication date: January 4, 2024
    Inventors: Kun YU, Changming LIU, Xinyu ZHANG
  • Publication number: 20230410535
    Abstract: A method for generating a lane line, and includes: acquiring three-dimensional point cloud data and two-dimensional lane line data of a target lane, the two-dimensional lane line data being lane line data collected in response to determining that the vehicle is driving in the target lane, and the three-dimensional point cloud data being point cloud data of the surrounding environment of the vehicle collected in response to determining that the vehicle is driving in the target lane; determining a plurality of lane line key points according to the two-dimensional lane line data and the three-dimensional point cloud data; and obtaining a target three-dimensional lane line by connecting the plurality of lane line key points randomly for many times according to attribute information of the plurality of lane line key points and a driving direction of the vehicle.
    Type: Application
    Filed: November 20, 2022
    Publication date: December 21, 2023
    Applicant: Xiaomi EV Technology Co., Ltd.
    Inventor: Kun YU
  • Publication number: 20230402551
    Abstract: Provided is a photovoltaic solar cell, a solar cell module and a manufacturing process. The photovoltaic solar cell includes a silicon substrate, and a passivation layer located on at least one surface of the silicon substrate. An electrode, an electrode pad and an extension line are printed on at least one surface of the silicon substrate. The electrode includes a busbar and a finger crossed with each other, and the finger is in contact with the silicon substrate. Two ends of the extension line are respectively connected to the busbar and the electrode pad, to reinforce a connection between the busbar and the electrode pad such that the extension line is not in direct contact with the finger, the extension line is in contact with the passivation layer, the electrode pad and the busbar are not in direct contact with the silicon substrate.
    Type: Application
    Filed: August 17, 2023
    Publication date: December 14, 2023
    Inventors: Xunlei YAN, Kun YU, Changming LIU, Xinyu ZHANG
  • Patent number: 11843071
    Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and a one-dimensional size of the top surface of the outermost first substructure is less than or equal to 45 ?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer, the doped conductive layer includes a P-type doped conductive layer and an N-type doped conductive layer; and a second passivation layer located on a surface of the doped conductive layer.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: December 12, 2023
    Assignees: Shanghai Jinko Green Energy Enterprise Management CO., LTD., Zhejiang Jinko Solar CO., LTD.
    Inventors: Kun Yu, Changming Liu, Xinyu Zhang
  • Publication number: 20230377991
    Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 23, 2023
    Inventors: Chien Lin, Kun-Yu Lee, Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang
  • Publication number: 20230376653
    Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 23, 2023
    Inventors: Hsin-Chuan Kuo, Chia-Wei Chen, Yu-Hsiu Lin, Kun-Yu Wang, Sheng-Tai Tseng, Chun-Ku Ting, Fang-Ming Yang, Yu-Hsien Ku, Jen-Wei Lee, Ronald Kuo-Hua Ho, Chun-Chieh Wang, Yi-Ying Liao, Tai-Lai Tung, Ming-Fang Tsai, Chun-Chih Yang, Chih-Wei Ko, Kun-Chin Huang
  • Patent number: 11821844
    Abstract: An artificial neural network-based method for detecting a surface type of an object includes: receiving a plurality of object images, wherein a plurality of spectra of the plurality of object images are different from one another and each of the object images has one of the spectra; transforming each object image into a matrix, wherein the matrix has a channel value that represents the spectrum of the corresponding object image; and executing a deep learning program by using the matrices to build a predictive model for identifying a target surface type of the object. Accordingly, the speed of identifying the target surface type of the object is increased, further improving the product yield of the object.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: November 21, 2023
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventor: Kun-Yu Tsai
  • Patent number: 11824136
    Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2 ?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: November 21, 2023
    Assignees: Shanghai Jinko Green Energy Enterprise Management Co., Ltd., Zhejiang Jinko Solar Co., Ltd.
    Inventors: Kun Yu, Changming Liu, Xinyu Zhang
  • Patent number: 11810777
    Abstract: Provided is a composite encapsulating material and a photovoltaic module encapsulated with the composite encapsulating material, which relate to the technical field of photovoltaic modules. At least a partial area of the composite encapsulating material includes a high insulation material, and the high insulation material includes polyimide, modifier and modified polyimide. The above technical solution can improve an insulation performance of the encapsulating material, reduce a blank area of an edge of the module, reduce a weight of the photovoltaic module, and further reduce comprehensive cost of the photovoltaic module.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: November 7, 2023
    Assignees: Jinko Green Energy (Shanghai) Management Co., LTD., ZHEJIANG JINKO SOLAR CO., LTD.
    Inventors: Kun Yu, Changming Liu, Xinyu Zhang, Beibei Gao, Zengzhi Ma
  • Patent number: 11784631
    Abstract: A resonance element supported by a bearing structure includes a crystal chip and an excitation electrode. The crystal chip includes a main surface having a support surface portion being in contact with the bearing structure. The excitation electrode is disposed on the main surface, has an electrode area, and includes an electrode indentation boundary partly encompassing the support surface portion. The electrode indentation boundary has a first boundary end and a second boundary end being opposite to the first boundary end. The electrode indentation boundary and a reference line segment defined by the first and the second boundary ends form an electrode indentation region having an indentation area. A ratio of the indentation area to the electrode area ranges from 0.05 to 0.2.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 10, 2023
    Assignee: TAI-SAW TECHNOLOGY CO., LTD.
    Inventors: Chia-Haur Rau, Kun-Yu Huang, Chi-Yun Chen
  • Patent number: 11776263
    Abstract: Techniques related to training and implementing a bidirectional pairing architecture for object detection are discussed. Such techniques include generating a first enhanced feature map for each frame of a video sequence by processing the frames in a first direction, generating a second enhanced feature map for frame by processing the frames in a second direction opposite the first, and determining object detection information for each frame using the first and second enhanced feature map for the frame.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Yan Hao, Zhi Yong Zhu, Lu Li, Ciyong Chen, Kun Yu
  • Patent number: 11768858
    Abstract: A method of a power user classification based on distributed K-means, a storage medium and a classification device are provided. The method includes: obtaining, by N load aggregators, power consumption data of power users managed by respective load aggregators; performing, by each load aggregator, a normalization operation on time series load data of the power users managed by the load aggregator; forming a N×N dimensional adjacency matrix A; performing K-means clustering on normalized time series load data, to obtain the respective centroids and user groups characterized by the respective centroids; sharing, by the respective load aggregators, the centroids and the number of users under the respective centroids based on the adjacency matrix A, and obtaining consistent centroids by multiple load aggregators; after an overall iteration ends, obtaining, by the respective load aggregators, the consistent centroids consistent with the K-means centroid based on global data, to realize user classification.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: September 26, 2023
    Assignees: XI'AN JIAOTONG UNIVERSITY, State Grid Jiangsu Electric Power Co. Ltd, Hohai University
    Inventors: Gengfeng Li, Yuxiong Huang, Liyin Zhang, Jiangfeng Jiang, Qirui Qiu, Shihai Yang, Xingying Chen, Xiaodong Cao, Kun Yu