Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

Abstract: The application discloses a method and a system for shaping flexible blocks on a chip canvas in an integrated circuit design. An input is received describing geometric features of flexible blocks. A set of flexible blocks are generated based on the input. Obtained block areas of the set of flexible blocks are computed. Whether the set of flexible blocks are legal is determined based on determining whether area differences between the obtained block areas and a plurality of required areas for the set of flexible blocks meet a requirement. The set of flexible blocks are updated until the set of flexible blocks are all legal.

Abstract: A resonant asymmetrical half-bridge flyback power converter includes: a first transistor and a second transistor switching a transformer coupled to a capacitor for generating an output power; a voltage divider coupled to an auxiliary winding of the transformer; a differential sensing circuit which includes a first terminal and a second terminal coupled to the voltage divider to sense an auxiliary signal generated by the auxiliary winding for generating a peak signal and a demagnetization-time signal; and a PWM control circuit configured to generate a first PWM signal and a second PWM signal in accordance with the peak signal and the demagnetization-time signal, for controlling the first transistor and the second transistor respectively; wherein a period of an enabling state of the demagnetization-time signal is correlated to the output power level; wherein the peak signal is related to a quasi-resonance of the transformer after the transformer is demagnetized.

Abstract: A surface plasmon resonance sensor is provided, which comprises: a substrate; an adaptation layer disposed on the substrate and comprising a dielectric material; and a metal layer disposed on the adaptation layer, wherein the metal layer has a grating structure comprising plural metal lines. Furthermore, a surface plasmon resonance sensing instrument comprising the same and a method for detecting an analyte using the same are also provided.

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Abstract: The present invention provides a wide-filed spectral imaging system including a laser generator, a wavelength adjustment module, an objective lens, and a single-pixel imaging and a spectral separating module. The laser generator is configured to generate a laser excitation beam. The wavelength adjustment module is configured to disperse the laser excitation beam into a plurality of beams of different wavelengths. The objective lens is configured to focus the plurality of beams of different wavelengths on a sample to excite molecules under test in the sample and generate an emission light. The single-pixel imaging and spectral separating module is configured to generate a series of patterns and modulate the emission light with the series of patterns to generate a diffracted beam. The single-pixel imaging and spectral separating module further disperses the wavelength of the diffracted beam, collects light signals of the expanded diffracted beam, and performs a spectral image reconstruction.

Abstract: A computerized simulation validating method for a full-scale distribution network single phase-to-ground fault test is implemented by simulating a full-scale test system with external quantities being controlled to be conformant and validating the full-scale distribution network single phase-to-ground fault test based on a conformance check result between the internal quantities of the field testing and the internal quantities of the simulation testing. The simulation validating method for a full-scale distribution network single phase-to-ground fault test improves normalization and conformance of the full-scale distribution network ground fault test. The computerized simulation validating system, apparatus, and medium for a full-scale distribution network single phase-to-ground fault test also achieve the benefits noted above.

Abstract: A detection device includes a substrate and a die. The substrate provides a first voltage. The die is disposed adjacent to the substrate. The die includes a plurality of resistor paths, a selection circuit, an ADC (Analog-to-Digital Converter), and a digital circuit. The selection circuit selects one of the resistor paths as a target path. The target path provides a second voltage. The ADC generates a digital signal according to the first voltage and the second voltage. The digital circuit processes the digital signal.

Abstract: The present invention relates to wheat plants comprising a mutation causing an alteration of the amino acid sequence in centromere histone H3 (CENH3), which have the biological activity of a haploid inducer. Further, the present invention provides methods of generating the wheat plants of the present invention and haploid and doubled haploid wheat plants obtainable by crossing the wheat plants of the present invention with wildtype wheat plants.

Abstract: A first data packet can be forwarded to a virtual SDWAN interface which has multiple IPSec tunnels as members, each of which is disposed over a different uplink, wherein the multiple IPSec tunnels each connect to the remote SDWAN controller. Load balancing of the particular session is performed relative to other sessions by selecting one of the multiple uplinks for transmission to the remote SDWAN controller. Phase 2 of IPSec is set up for the particular session by updating an IPSec phase 2 table with the selected uplink associated with the particular session, to direct subsequent packets of the same session.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has a U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: Digital content view control is described as leveraging a hierarchical structure of objects defined within the digital content to control how those objects are rendered in a user interface. In one example, a user input is received to display a view of objects within digital content displayed in a user interface. In response, a data query module is configured to fetch data describing a hierarchical structure of the digital content. From this, a z-order determination module determines a z-order of objects included with the digital content. An object view generation module is also configured to generate object views depicting the objects included in the digital content. The object views, once rendered, support an ability to view positioning of objects within the hierarchy.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: A composite intermediary device using vertical probe for wafer testing, comprising: a printed circuit board, a glass interposer and a vertical probe set; wherein the printed circuit board has printed circuit connected with a measuring apparatus, the glass interposer has multiple contact pads connected with the printed circuit, and then the probes of the vertical probe set are against the contact pads of the glass interposer and the bumps of the device under test. By a fine pitch configuration of the printed circuit and the contact pads of the glass interposer, the present invention achieves the requirements of synchronous and interleaved testing of multiple ICs.

Abstract: A computerized simulation validating method for a full-scale distribution network single phase-to-ground fault test is implemented by simulating a full-scale test system with external quantities being controlled to be conformant and validating the full-scale distribution network single phase-to-ground fault test based on a conformance check result between the internal quantities of the field testing and the internal quantities of the simulation testing. The simulation validating method for a full-scale distribution network single phase-to-ground fault test improves normalization and conformance of the full-scale distribution network ground fault test. The computerized simulation validating system, apparatus, and medium for a full-scale distribution network single phase-to-ground fault test also achieve the benefits noted above.

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.

Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.

Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.

Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.