Abstract: An area selection-based document object model element inspector is described. A dragging input that defines a selection area of a digital content document having a plurality of elements is received via an area selection-based inspector tool. A set of elements of the plurality of elements that is positioned within the selection area is selected. Details of the selected set of elements are broadcast for display.

Abstract: Various systems, devices, storage media, and methods are discussed for selecting communication paths based upon health status in a hub and spoke communication network.

Abstract: A composite intermediary device using vertical probe for wafer testing, comprising: a printed circuit board, a glass interposer and a vertical probe set; wherein the printed circuit board has printed circuit connected with a measuring apparatus, the glass interposer has multiple contact pads connected with the printed circuit, and then the probes of the vertical probe set are against the contact pads of the glass interposer and the bumps of the device under test. By a fine pitch configuration of the printed circuit and the contact pads of the glass interposer, the present invention achieves the requirements of synchronous and interleaved testing of multiple ICs.

Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: A solar cell includes a semiconductor substrate, in which a rear surface of the semiconductor substrate having non-pyramid-shaped microstructures, the non-pyramid-shaped microstructures include two or more first substructures at least partially stacked on one another, and a one-dimensional size of the surface of the outermost first substructure is less than or equal to 45 ?m; a first passivation layer located on a front surface of the semiconductor substrate; first and second tunnel oxide layers located on the non-pyramid-shaped microstructures; first and second doped conductive layers located on a surface of the first and second tunnel oxide layers, the first and second doped conductive layer has different conductive types; a second passivation layer located on a surface of the first and second doped conductive layers; and electrodes formed by penetrating through the second passivation layer to be in contact with the first and second doped conductive layers.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: A circuit of a resonant power converter comprising: a high-side switch and a low-side switch, coupled to form a half-bridge switching circuit which is configured to switch a transformer for generating an output voltage; a high-side drive circuit, generating a high-side drive signal coupled to drive the high-side switch in response to a high-side control signal; a bias voltage, coupled to a bootstrap diode and a bootstrap capacitor providing a power source from the bootstrap capacitor for the high-side drive circuit; wherein the high-side drive circuit generates the high-side drive signal with a fast slew rate to turn on the high-side switch when the high-side switch is to be turned on with soft-switching; the high-side drive circuit generates the high-side drive signal with a slow slew rate to turn on the high-side switch when the high-side switch is to be turned on without soft-switching.

Abstract: A power conversion apparatus includes an AC-DC conversion circuit, a power controller, and a circulating current controller. The power controller is configured to control the AC-DC conversion circuit to convert a received alternating current into a first direct current and output the first direct current. The circulating current controller is configured to send a synchronization signal to another power conversion apparatus through a controller area network (CAN) bus. The synchronization signal is used to synchronize a carrier of the another power conversion apparatus with a carrier of the power conversion apparatus.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a material layer over a semiconductor substrate; forming a plurality of spacer masks over the material layer; patterning the material layer into a plurality of masks below the spacer masks, wherein patterning the material layer comprises an atomic layer etching (ALE) process; and etching the semiconductor substrate through the masks.

Abstract: A device includes a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions. A metal-insulator-metal (MIM) structure is embedded in the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer. The third dielectric layer and the second dielectric layer have different material compositions. The first dielectric layer or the third dielectric layer may contain silicon nitride (SiN), the second dielectric layer may contain silicon oxide (SiO2).

Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices, and a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In some embodiments, the MIM capacitor structure includes a first conductor plate layer, an insulator layer on the first conductor plate layer, and a second conductor plate layer on the insulator layer. In some examples, the insulator layer includes a metal oxide sandwich structure.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: Systems and methods may be used for protecting healthy tissue in particle therapy. For example, a method may include defining a particle arc range for a radiotherapy treatment of a patient. The method may include generating a spot selection for an arc sequence, including a trajectory for delivering the radiotherapy treatment, for example, based on a temporal dose heterogeneity parameter or a spatial dose heterogeneity parameter. The method may include optimizing fluence of the arc sequence for the radiotherapy treatment, for example, based on an applied temporal dose heterogeneity specific cost function or an applied spatial dose heterogeneity specific cost function.

Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Abstract: A plurality of fake vulnerabilities are exposed to network traffic alongside an active resource. Each fake vulnerability cannot harm the active resource and wherein the deceptive proxy device and the legitimate device are reachable by a common IP address. Network traffic is monitored in real-time, to detect an attack by a malicious device concerning at least one of the fake vulnerabilities of the plurality of fake vulnerabilities exposed by the deceptive proxy resource. The malicious device is trusted by the enterprise network. Responsive to the attack detection, a security action is taken with respect to the malicious device.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: Provided are a solar cell, including: a semiconductor substrate, in which a rear surface of the semiconductor substrate having non-pyramid-shaped microstructures, the non-pyramid-shaped microstructures include two or more first substructures at least partially stacked on one another, and a one-dimensional size of the surface of the outermost first substructure is less than or equal to 45 ?m; a first passivation layer located on a front surface of the semiconductor substrate; first and second tunnel oxide layers located on the non-pyramid-shaped microstructures; first and second doped conductive layers located on a surface of the first and second tunnel oxide layers, the first and second doped conductive layer has different conductive types; a second passivation layer located on a surface of the first and second doped conductive layers; and electrodes formed by penetrating through the second passivation layer to be in contact with the first and second doped conductive layers.

Abstract: The present invention relates to wheat plants comprising a mutation causing an alteration of the amino acid sequence in centromere histone H3 (CENH3), which have the biological activity of a haploid inducer. Further, the present invention provides methods of generating the wheat plants of the present invention and haploid and doubled haploid wheat plants obtainable by crossing the wheat plants of the present invention with wildtype wheat plants.

Abstract: A system for detecting a surface type of an object includes a driver component, a driver component, and a plurality of photosensitive elements. The surface of the object is divided along a first direction into a plurality of areas, and the driver component sequentially moves one of the plurality of areas to a detection position. The light source component faces the detection position and provides light of a plurality of spectra that are different from one another to illuminate the detection position. The photosensitive elements face different sections of the area at the detection position, to capture detection images of different sections of the area located at the detection position under the light of each of the spectra. One photosensitive axis of the photosensitive elements is parallel to the normal line while another photosensitive axis of the photosensitive elements is between the normal line and the first direction.