Abstract: A resonant half-bridge flyback power converter includes: a power transformer and a resonant capacitor which are coupled in series between a half-bridge power stage and an output power; and a primary controller circuit controlling a high side power switch and a low side power switch of the half-bridge power stage. When the high side switch is OFF, the control signal of the low side power switch includes a resonant switching pulse for achieving resonant switching of the low side switch and a soft switching pulse for achieving ZVS of the high side switch. When the output power is lower than a delay threshold, the primary controller circuit determines a delay period which is between the resonant switching pulse and the soft switching pulse to control both the high side power switch and the low side power switch to be OFF. The delay period is negatively correlated with the output power.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Abstract: The present invention relates to a traffic situation detecting method. The method includes steps of acquiring a current location, a speed of movement and a direction of movement for a ground vehicle; using the current location as a starting point and drawing a detecting scope on a digital map toward the direction of movement; varying a size of the detecting scope in adaptive to an interval of the speed to which the speed of movement belongs; accessing a traffic server to retrieve a traffic event and determining whether the traffic event is situated within the detecting scope; and marking the traffic event located within the detecting scope on a digital map.

Abstract: System and techniques are provided for three-dimension (3D) semantic segmentation. A device for 3D semantic segmentation includes: an interface, to obtain a point cloud data set for a time-ordered sequence of 3D frames, the 3D frames including a current 3D frame and one or more historical 3D frames previous to the current 3D frame; and processing circuitry, to: invoke a first artificial neural network (ANN) to estimate a 3D scene flow field for each of the one or more historical 3D frames by taking the current 3D frame as a reference frame; and invoke a second ANN to: produce an aggregated feature map, based on the reference frame and the estimated 3D scene flow field for each of the one or more historical 3D frames; and perform the 3D semantic segmentation based on the aggregated feature map.

Abstract: There is disclosed a method for mitigating phishing risk to a recipient of a phishing electronic document. The method comprises receiving (302) the phishing electronic document (108) intended for the recipient (104) and identifying (304) parameters in the phishing electronic document. The parameters are applied (306) to a customised risk profile of the recipient to generate a risk index. The risk index is then compared (308) to a specified risk threshold. A phishing alert based on the comparison is generated (310) and provided (312) to the recipient along with the electronic document.

Abstract: System and methods may be used for arc fluence optimization without iteration to arc sequence generation. A method may include defining a particle arc range for a radiotherapy treatment of a patient, and generating an arc sequence, including a set of parameters for delivering the radiotherapy treatment, without requiring a dose calculation. The method may include optimizing fluence of the arc sequence for the radiotherapy treatment without iterating back to arc sequence generation, and outputting the fluence optimized arc sequence for use in the radiotherapy treatment.

Abstract: Systems, apparatuses and methods (30) may provide for technology that stores data associated with a plurality of intermediate operations in an autonomous vehicle process (32), generates a visualization output based at least partly on the data (34), and changes a magnification level of the visualization output based on user input (38), the visualization output is generated further based on parameter input and the data includes vector chart data.

Abstract: Techniques related to training and implementing a bidirectional pairing architecture for object detection are discussed. Such techniques include generating a first enhanced feature map for each frame of a video sequence by processing the frames in a first direction, generating a second enhanced feature map for frame by processing the frames in a second direction opposite the first, and determining object detection information for each frame using the first and second enhanced feature map for the frame.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a first side, a second side opposite to the first side, and at least one light-sensing region close to the first side. The image sensor device includes a dielectric feature covering the second side and extending into the semiconductor substrate. The dielectric feature in the semiconductor substrate surrounds the light-sensing region. The image sensor device includes a reflective layer in the dielectric feature in the semiconductor substrate, wherein a top portion of the reflective layer protrudes away from the second side, and a top surface of the reflective layer and a top surface of the insulating layer are substantially coplanar.

Abstract: The invention relates to a universal semiconductor automatic high-speed serial signal testing method, comprising: a chip to be tested sending, to an impedance matching unit, a high-speed serial signal; then by means of a phase shift unit, sequentially transforming, according to a set fixed resolution, the phase of the high-speed serial signal, the magnitude of each offset phase being determined by a phase shift control signal outputted by a control unit and the resolution of the phase shift unit; after passing through the phase shift unit, the high-speed serial signal keeps channel impedance matching by means of the impedance matching unit; the signal entering an acquisition unit, and being acquired under the action of an acquisition control signal sent by the control unit; the control unit performing signal exchange with semiconductor automatic testing equipment (ATE); and the acquisition unit transmitting the acquired signal back to the universal semiconductor ATE for algorithm operation, and then the actua

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: System and methods may be used for arc fluence optimization without iteration to arc sequence generation. A method may include defining a particle arc range for a radiotherapy treatment of a patient, and generating an arc sequence, including a set of parameters for delivering the radiotherapy treatment, without requiring a dose calculation. The method may include optimizing fluence of the arc sequence for the radiotherapy treatment without iterating back to arc sequence generation, and outputting the fluence optimized arc sequence for use in the radiotherapy treatment.

Abstract: An embodiment of the present disclosure provides an array substrate, a display panel, and a display device, including a substrate, a data line located above the substrate, and a shielding member located on a side, away from the substrate, of the data line, the shielding member includes a conductive screening portion, an orthographic projection of the conductive screening portion on the substrate partially covering an orthographic projection of the data line on the substrate, or the shielding member includes a filling body, an orthographic projection of the filling body on the substrate covering an orthographic projection of the data line on the substrate, and the filling body protruding outward from a surface of the substrate in a direction away from the substrate.

Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.

Abstract: A vehicular image pickup device includes an image capturing unit and a processing unit. The image capturing unit captures a plurality of driving images sequentially. The driving images each include an object image. The processing unit performs an image analysis on two of the plurality of driving images to obtain a variance of the object image and sets a shutter speed of the image capturing unit according to the variance.

Abstract: A diode, which is implemented in a semiconductor structure, includes a substrate, and first, second, third and fourth conductors. The substrate contains first and second doped regions. The first and second doped regions are used respectively as a first electrode and a second electrode of the diode. The first and third conductors are in a first conductor layer of the semiconductor structure and are connected to the first and second doped regions, respectively. The second and fourth conductors are in a second conductor layer of the semiconductor structure and are connected to the first and third conductors, respectively. In a side view of the semiconductor structure, an overlapping area between the first conductor and the third conductor is larger than an overlapping between of the second conductor and the fourth conductor.

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

Abstract: A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

Abstract: A method for skin care and/or maintenance including applying or administering a preparation to a subject is provided. The preparation includes a biomedical composition, and the biomedical composition includes an effective amount of micelle, wherein the micelle includes a hyaluronic acid and/or a derivative thereof and a modified histidine. The modified histidine is grafted to at least one primary hydroxyl group of the hyaluronic acid and/or the derivative thereof, and a graft ratio of the modified histidine is 1-100%. Moreover, the hyaluronic acid and/or the derivative thereof and the modified histidine form the micelle on a weight percentage of 0.2-300:1.