Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a material layer over a semiconductor substrate; forming a plurality of spacer masks over the material layer; patterning the material layer into a plurality of masks below the spacer masks, wherein patterning the material layer comprises an atomic layer etching (ALE) process; and etching the semiconductor substrate through the masks.

Abstract: Provided is a photovoltaic solar cell, a solar cell module and a manufacturing process. The photovoltaic solar cell includes a silicon substrate, and a passivation layer located on at least one surface of the silicon substrate. An electrode, an electrode pad and an extension line are printed on at least one surface of the silicon substrate. The electrode includes a busbar and a finger crossed with each other, and the finger is in contact with the silicon substrate. Two ends of the extension line are respectively connected to the busbar and the electrode pad, and the extension line is in contact with the silicon substrate.

Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2 ?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.

Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: An ester compound which can be used as the additive of the lubricating oil or the base oil of the lubricating oil, and a process for preparing the same and use thereof are provided. The ester has excellent viscosity-temperature properties and low-temperature properties and can be used as the base oil of the lubricating oil. In addition, the ester compound has excellent viscosity-temperature properties and low-temperature properties as the viscosity index improver, can significantly reduce the wear scar diameter of the base oil as the anti-wear agent, can significantly reduce the friction coefficient of the base oil as the friction modifier, and exhibits excellent anti-wear and anti-friction properties.

Abstract: A DNS (Domain Name Server) proxy is configured as a DNS server for clients on the enterprise network to send two or more DNS queries to collect each available IP addresses on a SDWAN member link. IP address collection can be responsive to receiving a DNS request from a client for assigning a FQDN (Fully Qualified Domain Name). Service quality can be evaluated for the service on each member link of the IP addresses. An IP address is assigned to the client based on the service quality evaluation. A notification is transmitted to the client in a DNS response to the IP address request, with the chosen IP address information for configuration.

Abstract: A flyback power converter circuit includes a transformer, a blocking switch, a primary side switch, a primary side controller circuit and a secondary side controller circuit. The transformer is coupled between an input voltage and an internal output voltage in an isolated manner. The blocking switch controls the electric connection between the internal output voltage and an external output voltage. In a standby mode, the internal output voltage is regulated to a standby voltage, and the blocking switch is controlled to be OFF; in an operation mode, the internal output voltage is regulated to an operating voltage, and the blocking switch is controlled to be ON, such that the external output voltage has the operating voltage. The standby voltage is smaller than the operating voltage, so that the power consumption of the flyback power converter circuit is reduced in the standby mode.

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Abstract: A structure and formation method of a semiconductor device is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Abstract: A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

Abstract: A flyback converter includes a power transformer, a primary side switch, a secondary side switch and a controller. A secondary side switching signal has an SR pulse for achieving synchronous rectification, and a ZVS pulse for achieving zero voltage switching. The ZVS pulse is enabled according to a first characteristic of a resonance waveform, whereas, a primary side switching signal is enabled according to a second characteristic of resonance waveform. When an output current increases, the primary side switching signal is disabled during an inhibition interval, such that primary side switching signal does not overlap with the ZVS pulse, thereby preventing the primary and secondary side switches from being both conductive simultaneously. The inhibition interval is correlated with a rising edge of the primary side switching signal in a previous switching period and a resonance period of the resonance waveform.

Abstract: An embodiment of the present disclosure provides an array substrate, a display panel, and a display device, including a substrate, a data line located above the substrate, and a shielding member located on a side, away from the substrate, of the data line, the shielding member includes a conductive screening portion, an orthographic projection of the conductive screening portion on the substrate partially covering an orthographic projection of the data line on the substrate, or the shielding member includes a filling body, an orthographic projection of the filling body on the substrate covering an orthographic projection of the data line on the substrate, and the filling body protruding outward from a surface of the substrate in a direction away from the substrate.

Abstract: A flyback power converter circuit includes: a power transformer, a primary side switch and a conversion control circuit. In a DCM, during a dead time, the conversion control circuit calculates an upper limit frequency corresponding to output current according to a frequency upper limit function, and obtains a frequency upper limit masking period according to a reciprocal of the upper limit frequency, wherein the frequency upper limit masking period is a period starting from when the primary side switch is turned ON. During an upper limit selection period, the conversion control circuit selects a valley among one or more valleys in a ringing signal related to a voltage across the primary side switch as an upper limit locked valley, so that the conversion control circuit once again turns ON the primary side switch at a beginning time point of the upper limit locked valley.

Abstract: A resonance element supported by a bearing structure includes a crystal chip and an excitation electrode. The crystal chip includes a main surface having a support surface portion being in contact with the bearing structure. The excitation electrode is disposed on the main surface, has an electrode area, and includes an electrode indentation boundary partly encompassing the support surface portion. The electrode indentation boundary has a first boundary end and a second boundary end being opposite to the first boundary end. The electrode indentation boundary and a reference line segment defined by the first and the second boundary ends form an electrode indentation region having an indentation area. A ratio of the indentation area to the electrode area ranges from 0.05 to 0.2.

Abstract: A display panel, a mask plate, a method for manufacturing the display panel, and a display device are provided. The display panel includes a display area and a peripheral area surrounding the display area, and the display panel further includes: at least two integrated chips located in the peripheral area of the display area and arranged along a boundary direction of the display area; at least one flow rate regulating structure is respectively located between two adjacent integrated chips and located on a side of the integrated chips remote from the display area, and the flow rate regulating structure is configured to adjust a flow rate of process liquid.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: Techniques related to training and implementing a bidirectional pairing architecture for object detection are discussed. Such techniques include generating a first enhanced feature map for each frame of a video sequence by processing the frames in a first direction, generating a second enhanced feature map for frame by processing the frames in a second direction opposite the first, and determining object detection information for each frame using the first and second enhanced feature map for the frame.