Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a plurality of nanowires. The substrate has an upper surface. The nanowires are stacked on the upper surface of the substrate along a first direction. The nanowires include a triangle in a cross section, and the nanowires include a plane extending along a second direction, a first down-slant facet on a (111) plane, and a second down-slant facet on an additional (111) plane.

Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

Abstract: Disclosed are a dual-optical-path spectrophotometer and a color measurement method thereof. The spectrophotometer includes an integrating sphere, a light source, and a sensor. A second shutter, a semi-reflecting and semi-transmitting device and lenses are arranged between the detection hole and the sensor, and a light guide device and a first shutter are arranged between a light guide hole formed in the integrating sphere and the semi-reflecting and semi-transmitting device. The color measurement method includes the following steps. A first shutter is closed, a second shutter is opened, light, reflected by the measuring opening, enters a sensor and the sensor measures a spectral reflected signal of the object surface. The first shutter is opened, the second shutter is closed, reflected light enters the sensor, and the sensor measures a spectral reflected signal of a light source. A final sampled signal is calculated.

Abstract: Sulfonyl-triazole compounds and related sulfonyl-heterocycle compounds are described. The compounds can be used to identify reactive nucleophilic amino acid residues, such as reactive tyrosines and reactive lysines, in proteins and to modify the activity of proteins with reactive nucleophilic amino acid residues via the formation of protein adducts comprising a fragment of the compounds. Methods are also described for screening the compounds to identify ligands of proteins comprising a reactive lysine or a reactive tyrosine.

Abstract: Disclosed are a colorimeter and a reflectivity measuring method based on a multichannel spectrum. The colorimeter includes a main unit and a calibration box, wherein the main unit includes an integrating sphere, a light source and a main sensor, a detection hole is formed in one side of a top of the integrating sphere, a light-through hole is formed in a side of the integrating sphere, and a measuring port is formed in a bottom of the integrating sphere, the light source is arranged outside the light-through hole, and the main sensor is arranged outside the detection hole; the calibration box includes a housing and a white board arranged at a top of the housing, the white board is correspondingly matched with the measuring port, and the calibration box is connected with the main unit; the sensor is a multichannel spectral sensor.

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

Abstract: The present invention provides a snorkel having smaller respiratory dead space or volume. The snorkel includes a mouthpiece and a tube with an inhalation lumen and an exhalation lumen. A distal one-way inhalation valve is placed inside the inhalation lumen; and a distal one-way exhalation valve is placed inside the exhalation lumen. The invention also provides a method for reducing the volume of a respiratory dead space in a snorkel.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Abstract: A sample selection method and apparatus and a server belong to the field of metric learning technologies. The method includes: selecting n sample pairs from an unlabeled sample set, each sample pair including two samples, and each sample including data in p modalities; calculating a partial similarity between data that is in each modality and that is of one sample included in the sample pair and data that is in each modality and that is of the other sample, to obtain p×p partial similarities; calculating, according to the p×p partial similarities, an overall similarity between the two samples included in the sample pair; obtaining a degree of difference between the p×p partial similarities and the overall similarity; and selecting a sample pair that meets a preset condition and that is in the n sample pairs as a training sample.

Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

Abstract: The present invention provides a snorkel having smaller respiratory dead space or volume. The snorkel includes a mouthpiece and a tube with an inhalation lumen and an exhalation lumen. A distal one-way inhalation valve is placed inside the inhalation lumen; and a distal one-way exhalation valve is placed inside the exhalation lumen. The invention also provides a method for reducing the volume of a respiratory dead space in a snorkel.

Abstract: The present invention provides a snorkel having smaller respiratory dead space or volume. The snorkel includes a mouthpiece and a tube with an inhalation lumen and an exhalation lumen. A distal one-way inhalation valve is placed inside the inhalation lumen; and a distal one-way exhalation valve is placed inside the exhalation lumen. The invention also provides a method for reducing the volume of a respiratory dead space in a snorkel.