Patents by Inventor Kun Yuan

Kun Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9696825
    Abstract: The method includes the steps of: a) connecting a handheld touchscreen computer with a first display to a personal computer with a second display and mouse, wherein a screen picture of the handheld touchscreen computer is projected on the second display as a subwindow, and a cursor is shown on the second display; b) directly moving the cursor by the mouse when no item in the subwindow is clicked; c) calculating a displacement quantity of the cursor against a virtual origin of the subwindow when an item in the subwindow is being clicked; and d) generating a mouse event to an item of the handheld touchscreen computer at a position corresponding to the displacement quantity.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: July 4, 2017
    Assignee: I/O INTERCONNECT, LTD.
    Inventors: Kun-Yuan Lin, Chung-Han Hsieh
  • Patent number: 9685531
    Abstract: A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Patent number: 9673100
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: June 6, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Chien-Ting Lin, Shih-Fang Tzou, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
  • Publication number: 20170133274
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.
    Type: Application
    Filed: December 8, 2015
    Publication date: May 11, 2017
    Inventors: Chia-Lin Lu, Shih-Fang Tzou, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Publication number: 20170125291
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
  • Patent number: 9640484
    Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: May 2, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Hsien Lin, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Publication number: 20170117380
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Publication number: 20170102129
    Abstract: There is provided a lighting device (100) comprising a first tubular body (120), a second tubular body (130) within the first tubular body (120), and a support structure within the first tubular body (120). The support structure supports a plurality of Solid State Lighting (SSL) elements (160) on a support surface, said SSL elements being arranged to emit light under a range of angles including a first range. The support structure is fixed within the first tubular body (120) by the first tubular body (120) and the second tubular body (130). The support structure comprises a tube receiving member (156) extending from the support surface, said tube receiving member engaging with the second tubular body (130).
    Type: Application
    Filed: January 29, 2015
    Publication date: April 13, 2017
    Applicant: PHILIPS LIGHTING HOLDING B.V.
    Inventor: MOU KUN YUAN
  • Publication number: 20170087399
    Abstract: The present invention provides exercise apparatus comprising a first handle, an elongated connector, an extension director, a second handle, a rod, and an elongated elastic member having a first end and a second end. The extension director is configured to direct the first end of the elongated elastic member to move to a first direction when the elastic member is stretched by pushing the first handle and the second handle closer to each other, and to a second direction when the elastic member is stretched by pulling the first handle and the second handle away from each other.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Inventor: Kun Yuan Tong
  • Patent number: 9604377
    Abstract: When two conventional safety razor double-edged blades are superposed on top of each other, there is no space in between them to pass the shaving residues. The presently invented safety razor double-edged blade is equipped with several spaced protuberances on its surface. When two of these present invented blades are overlapped, there is a space between them to pass the shaving residues to be rinsed away by running water. Therefore two, three or more of them can be superposed on a single razor blade holder to allow the user to experience all the benefits of a multi-blade razor cartridge in a safety razor blade system.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 28, 2017
    Inventor: Kun Yuan Tong
  • Publication number: 20170084722
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.
    Type: Application
    Filed: October 21, 2015
    Publication date: March 23, 2017
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Wei-Hao Huang
  • Publication number: 20170083344
    Abstract: A method for transferring an input device of a computer to a mobile device is provided herein. The computer has a first port actuated by a first driver for coupling to the input device. The method includes steps of: (a) detecting whether the mobile device is connected to the computer through a second port, to proceed to step (b) if they are connected, or to repeat step (a) if they are not connected; (b) installing a second driver to substitute for the first driver to control the second port; (C) sending a command to the mobile device to make the computer as an accessory device; (d) transferring the control right of the input device to the mobile device; and (e) getting an input signal through the first port, converting the input signal through the second driver, and sending the converted input signal to the mobile device through the second port.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 23, 2017
    Inventors: Ping-Shun ZEUNG, Kun-Yuan LIN
  • Publication number: 20170077031
    Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.
    Type: Application
    Filed: October 13, 2015
    Publication date: March 16, 2017
    Inventors: Chia-Lin Lu, Chun-Hsien Lin, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Publication number: 20170069528
    Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: Wei-Hao Huang, Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen, Shang-Yuan Tsai
  • Patent number: 9583388
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: February 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
  • Patent number: 9555279
    Abstract: The adjustable variant resistance exercise apparatus has installed several different resistant elastic springs and can provide variety of resistance for exercise. Man, woman, boy and girl can share the same one of adjustable variant resistance exercise apparatus for exercise. User can upgrade or downgrade exercise resistant power by adding more or remove some elastic rubber bands for exercise.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 31, 2017
    Inventor: Kun Yuan Tong
  • Patent number: 9543211
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Yu-Cheng Tung, Kun-Yuan Liao, Feng-Yi Chang, En-Chiuan Liou, Wei-Hao Huang, Chih-Sen Huang, Ching-Wen Hung
  • Patent number: 9543203
    Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, En-Chiuan Liou, Chia-Hsun Tseng, Wei-Hao Huang, Yu-Ting Hung
  • Publication number: 20170004997
    Abstract: A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.
    Type: Application
    Filed: July 2, 2015
    Publication date: January 5, 2017
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, En-Chiuan Liou, Chia-Hsun Tseng, Wei-Hao Huang, Yu-Ting Hung
  • Publication number: 20160380077
    Abstract: A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 29, 2016
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang