Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a fin-shaped structure on the MOSCAP region, forming a shallow trench isolation (STI) around the substrate and the fin-shaped structure, performing a first etching process to remove part of the STI on the MOSCAP region, and then performing a second etching process to remove part of the STI on the non-MOSCAP region and the MOSCAP region.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, performing a monolayer doping (MLD) process on the first fin-shaped structure, and then performing an anneal process for driving dopants into the first fin-shaped structure. Preferably, the MLD process is further accomplished by first performing a wet chemical doping process on the first fin-shaped structure and then forming a cap layer on the non-MOSCAP region and the MOSCAP region.

Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, wherein certain of the metal isolation features extend through the substrate to provide for full isolation between adjacent photodetectors and certain of the metal isolation features extend partially through the semiconductor layer to provide partially isolation between adjacent photodetectors.

Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.

Abstract: A circuit of a resonant power converter comprising: a high-side switch and a low-side switch, coupled to form a half-bridge switching circuit which is configured to switch a transformer for generating an output voltage; a high-side drive circuit, generating a high-side drive signal coupled to drive the high-side switch in response to a high-side control signal; a bias voltage, coupled to a bootstrap diode and a bootstrap capacitor providing a power source from the bootstrap capacitor for the high-side drive circuit; wherein the high-side drive circuit generates the high-side drive signal with a fast slew rate to turn on the high-side switch when the high-side switch is to be turned on with soft-switching; the high-side drive circuit generates the high-side drive signal with a slow slew rate to turn on the high-side switch when the high-side switch is to be turned on without soft-switching.

Abstract: A bidirectional electrostatic discharge protection device includes at least one bipolar junction transistor and at least one silicon-controlled rectifier. The silicon-controlled rectifier is coupled to the bipolar junction transistor in series. The absolute value of the breakdown voltage of the bipolar junction transistor is lower than that of the silicon-controlled rectifier and the absolute value of the holding voltage of the bipolar junction transistor is higher than that of the silicon-controlled rectifier when an electrostatic discharge voltage is applied to the bipolar junction transistor and the silicon-controlled rectifier.

Abstract: A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.

Abstract: A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

Abstract: A transient voltage suppression device includes at least one N-type lightly-doped structure, a first P-type well, a second P-type well, a first N-type heavily-doped area, and a second N-type heavily-doped area. The first P-type well and the second P-type well are formed in the N-type lightly-doped structure. The first N-type heavily-doped area and the second N-type heavily-doped area are respectively formed in the first P-type well and the second P-type well. The doping concentration of the first P-type well is higher than that of the second P-type well. The first P-type well and the second P-type well can be replaced with P-type lightly-doped wells respectively having P-type heavily-doped areas under the N-type heavily-doped areas.

Abstract: An ESD protection device includes an N-type semiconductor substrate, a P-type semiconductor layer, a first N-type well, a P-type well, a second N-type well, a first P-type heavily-doped area, a first N-type heavily-doped area, and a second P-type heavily-doped area. The semiconductor layer is formed on the substrate. The wells are formed in the semiconductor layer. The second N-type well directly touches the substrate. The first P-type heavily-doped area is formed in the first N-type well. The first N-type heavily-doped area and the second P-type heavily-doped area are formed in the P-type well. The second P-type heavily-doped area is coupled to the second N-type well through an external conductive wire and replaced with a second N-type heavily-doped area.

Abstract: A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

Abstract: A method for producing a probe card comprises the steps of: providing a carrier board, wherein a surface of the carrier board has at least one probe guiding portion; and generating a probe on the probe guiding portion by performing additive manufacturing with a conductive material directly on the at least one probe guiding portion to generate the probe, wherein the additive manufacturing comprises directly layering the conductive material on the probe guiding portion.

Abstract: A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

Abstract: State estimation and sensor fusion switching methods for autonomous vehicles thereof are provided. The autonomous vehicle includes at least one sensor, at least one actuator and a processor, and is configured to transfer and transport an object. In the method, a task instruction for moving the object and data required for executing the task instruction are received. The task instruction is divided into a plurality of work stages according to respective mapping locations, and each of the work stages is mapped to one of a transport state and an execution state, so as to establish a semantic hierarchy. A current location of the autonomous vehicle is detected by using the sensor and mapped to one of the work stages in the semantic hierarchy, so as to estimate a current state of the autonomous vehicle.

Abstract: A bidirectional electrostatic discharge protection device includes at least one bipolar junction transistor and at least one silicon-controlled rectifier. The silicon-controlled rectifier is coupled to the bipolar junction transistor in series. The absolute value of the breakdown voltage of the bipolar junction transistor is lower than that of the silicon-controlled rectifier and the absolute value of the holding voltage of the bipolar junction transistor is higher than that of the silicon-controlled rectifier when an electrostatic discharge voltage is applied to the bipolar junction transistor and the silicon-controlled rectifier.

Abstract: A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.

Abstract: A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.

Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

Abstract: A voucher verification auxiliary method is provided, including: when a user device is approaching a voucher verification auxiliary device, generating an encryption key for the user device to encrypt voucher data with the encryption key to generate first encrypted data; reading and decrypting the first encrypted data to obtain the voucher data; encrypting the voucher data to generate and transmit second encrypted data to a verification center; decrypting the second encrypted data to obtain the voucher data, generating a verification result after verifying the voucher data, encrypting the verification result to become third encrypted data, and transmitting the third encrypted data back to the voucher verification auxiliary device; decrypting the third encrypted data to obtain the verification result; transmitting the verification result to a voucher receiving terminal. A voucher verification auxiliary device and a voucher verification auxiliary system are also provided.

Abstract: A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.