Patents by Inventor Kunihiko Nishi

Kunihiko Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6291273
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: September 18, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Publication number: 20010015327
    Abstract: In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are sealed, by heat-sealing, in a bag moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging. The devices are packaged in a moisture-proofing bag made of a laminate film, and a desiccant is sealed, by heat-sealing the bag, in the moisture-proofing bag together with the, e.g., surface mount semiconductor device having a plastic package encapsulating the semiconductor device. A caution is provided for the bag, that the devices should be presented from moisture absorption after opening the bag.
    Type: Application
    Filed: April 30, 2001
    Publication date: August 23, 2001
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Publication number: 20010010949
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Application
    Filed: April 11, 2001
    Publication date: August 2, 2001
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Publication number: 20010008302
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Application
    Filed: January 30, 2001
    Publication date: July 19, 2001
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Publication number: 20010008304
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 25, 2001
    Publication date: July 19, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20010007781
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 30, 2001
    Publication date: July 12, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20010005055
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 30, 2001
    Publication date: June 28, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20010004127
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 30, 2001
    Publication date: June 21, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20010003059
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 29, 2001
    Publication date: June 7, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20010002730
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 22, 2001
    Publication date: June 7, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20010002724
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 29, 2001
    Publication date: June 7, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20010003048
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 25, 2001
    Publication date: June 7, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20010002064
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 17, 2001
    Publication date: May 31, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki
  • Publication number: 20010002069
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Application
    Filed: January 19, 2001
    Publication date: May 31, 2001
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Patent number: 6223893
    Abstract: In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are sealed, by heat-sealing, in a bag moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging. The devices are packaged in a moisture-proofing bag made of a laminate film, and a desiccant is sealed, by heat-sealing the bag, in the moisture-proofing bag together with the, e.g., surface mount semiconductor device having a plastic package encapsulating the semiconductor device.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: May 1, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Wahei Kitamura, Gen Murakami, Kunihiko Nishi
  • Publication number: 20010000079
    Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406).
    Type: Application
    Filed: December 5, 2000
    Publication date: March 29, 2001
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Kunihiko Nishi
  • Patent number: 6204552
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6169325
    Abstract: To realize low-profile electronic apparatus (a memory module and a memory card) of a large storage size by mounting tape carrier packages (TCPs) with a memory chip encapsulated onto a wiring board in high density. To be more specific, a TCP is composed of an insulating tape, leads formed on one side thereof, a potting resin with a semiconductor chip encapsulated, and a pair of support leads arranged on two opposite short sides. The pair of support leads function to hold the TCP at a constant tilt angle relative to the mounting surface of the wiring board. By varying the length vertical to the mounting surface, the TCP can be mounted to a desired tilt angle.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: January 2, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shuichiro Azuma, Takayuki Okinaga, Takashi Emata, Tomoaki Kudaishi, Tamaki Wada, Kunihiko Nishi, Masachika Masuda, Toshio Sugano
  • Patent number: 6166911
    Abstract: Provided is a semiconductor assembly, comprising a circuit board (1) including a conductor circuit (4), the conductor circuit including connecting pads, a semiconductor chip (2) provided with connecting terminals provided on a first surface thereof, and mounted on the circuit board, a casing (5) covering the circuit board, wherein the connecting pads of the conductor circuit and the connecting terminals of the semiconductor chip are disposed in mutually opposing relationship, and are connected with each other by an electroconductive bonding agent, a neutral plane of the semiconductor chip substantially coinciding with an overall neutral plane of the semiconductor assembly.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: December 26, 2000
    Assignees: Hitachi, Ltd., Hitachi Chemical Company, Ltd.
    Inventors: Mitsuo Usami, Kunihiko Nishi, Yoshikatsu Mikami, Masakatsu Suzuki
  • Patent number: 6162701
    Abstract: A semiconductor chip (105') and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406).The semiconductor chip (105') is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105') is hot-pressed by means of a heating head (106) for bonding on the substrate (102).In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: December 19, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, kunihiro Tsubosaki, Kunihiko Nishi